// *********************************************************************************
// Project Name : zkx2024
// Author       : Jlan
// Email        : 15533610762@163.com
// Create Time  : 2024-04-16
// File Name    : sram_table_top.v
// Module Name  : sram_table_top
// Called By    : jlan
// Abstract     : sram_table_top
//
// 
// *********************************************************************************
// Modification History:
// Date         By              Version                 Change Description
// -----------------------------------------------------------------------
// 2024-04-16    Macro           1.0                     Original
//  
// *********************************************************************************

module sram_table_top(
    input               CLK,
    input               RST_N,
    wraddr_st_bus.st    wa_s_0,
    wraddr_st_bus.st    wa_s_1,
    wraddr_st_bus.st    wa_s_2,
    wraddr_st_bus.st    wa_s_3,
    cc_st_bus.st        cc_s,
    raddr_st_bus.st     ra_s,
    st_cac_bus.st       s_cac_0,
    st_cac_bus.st       s_cac_1,
    st_cac_bus.st       s_cac_2,
    st_cac_bus.st       s_cac_3,
    st_cac_bus.st       s_cac_4,
    st_cac_bus.st       s_cac_5,
    st_cac_bus.st       s_cac_6,
    st_cac_bus.st       s_cac_7,
    st_imc_bus.st       s_imc_00,
    st_imc_bus.st       s_imc_01,
    st_imc_bus.st       s_imc_02,
    st_imc_bus.st       s_imc_03,
    st_imc_bus.st       s_imc_10,
    st_imc_bus.st       s_imc_11,
    st_imc_bus.st       s_imc_12,
    st_imc_bus.st       s_imc_13,
    st_imc_bus.st       s_imc_20,
    st_imc_bus.st       s_imc_21,
    st_imc_bus.st       s_imc_22,
    st_imc_bus.st       s_imc_23,
    st_imc_bus.st       s_imc_30,
    st_imc_bus.st       s_imc_31,
    st_imc_bus.st       s_imc_32,
    st_imc_bus.st       s_imc_33,
    st_imc_bus.st       s_imc_40,
    st_imc_bus.st       s_imc_41,
    st_imc_bus.st       s_imc_42,
    st_imc_bus.st       s_imc_43,
    st_imc_bus.st       s_imc_50,
    st_imc_bus.st       s_imc_51,
    st_imc_bus.st       s_imc_52,
    st_imc_bus.st       s_imc_53,
    st_imc_bus.st       s_imc_60,
    st_imc_bus.st       s_imc_61,
    st_imc_bus.st       s_imc_62,
    st_imc_bus.st       s_imc_63,
    st_imc_bus.st       s_imc_70,
    st_imc_bus.st       s_imc_71,
    st_imc_bus.st       s_imc_72,
    st_imc_bus.st       s_imc_73,
    st_tx_dd_bus.master s_tx
);
//-----------------------------------parameter----------------------------------------------//
parameter FIX_SRAM_ADDR =   4'h0;
//-----------------------------------inter_signal_define------------------------------------//
//sram_cfg_signal
logic   [4:0]   sram_table  [3:0];
logic   [0:0]   sram_active_0;
logic   [0:0]   sram_active_1;
logic   [0:0]   sram_active_2;
logic   [0:0]   sram_active_3;
logic   [0:0]   sram_active_0_r;
logic   [0:0]   sram_active_1_r;
logic   [0:0]   sram_active_2_r;
logic   [0:0]   sram_active_3_r;
logic   [0:0]   sram_empty_1;
logic   [0:0]   sram_empty_2;
logic   [0:0]   sram_empty_3;
logic   [0:0]   sram_empty_1_r;
logic   [0:0]   sram_empty_2_r;
logic   [0:0]   sram_empty_3_r;
logic   [7:0]   sram_full_0;
logic   [7:0]   sram_full_1;
logic   [7:0]   sram_full_2;
logic   [7:0]   sram_full_3;
//cache_fsm_signal
logic   [3:0]   cache_en;
logic   [3:0]   cache_en_pre;
logic   [31:0]  st_vld_data;
logic   [1:0]   cc_port_0;//instand of cc_port_0 will be write in which sram.
logic   [1:0]   cc_port_1;
logic   [1:0]   cc_port_2;
logic   [1:0]   cc_port_3;
logic   [1:0]   port;// port instand of current poket occuoy which sram.
logic   [2:0]   fix_pri;
logic   [2:0]   s1_pri;
logic   [2:0]   s2_pri;
logic   [2:0]   s3_pri;
logic   [9:0]   fix_size;
logic   [9:0]   s1_size;
logic   [9:0]   s2_size;
logic   [9:0]   s3_size;
typedef enum {  IDLE,
                GET_ADDR,
                TRAN_ADDR,
                TRAN_DATA
}   cache_st_t;

cache_st_t  sram_cache_c_0,
            sram_cache_n_0,
            sram_cache_c_1,
            sram_cache_n_1,
            sram_cache_c_2,
            sram_cache_n_2,
            sram_cache_c_3,
            sram_cache_n_3;
logic   [31:0] cc_req_data_r;
logic   [7:0]  cc_req;
logic   [7:0]  st_vld;
//st_vld_data is sram can write.
typedef enum {RVIDLE,
              FIX,
              SHARE_1,
              SHARE_2,
              SHARE_3
          } rv_fsm_t; 

rv_fsm_t    rv_fsm_c,rv_fsm_n;
//get_addr
logic   [0:0]   get_addr_0;//
logic   [0:0]   get_addr_1;//
logic   [0:0]   get_addr_2;//
logic   [0:0]   get_addr_3;//
logic   [17:0]  fix_addr;
logic   [17:0]  s1_addr;
logic   [17:0]  s2_addr;
logic   [17:0]  s3_addr;
//tran_addr
logic   [0:0]   tran_addr_done_0;///
logic   [0:0]   tran_addr_done_1;///
logic   [0:0]   tran_addr_done_2;///
logic   [0:0]   tran_addr_done_3;///
////write_done
//logic   [0:0]   write_done_0;
//logic   [0:0]   write_done_1;
//logic   [0:0]   write_done_2;
//logic   [0:0]   write_done_3;
//read logic
typedef enum {RDIDLE,
              RDJUDGE,
              RDGET_ADDR,
              BACK_ADDR,
              RD,
              JUMP} rd_st_t;
rd_st_t read_st_c,read_st_n;
logic   [0:0]   cur_cache_empty;
//dd logic
typedef enum {DDIDLE,
              JUDGE,
              FLUSH,
              DIR_DEL} dd_st_t;
dd_st_t dd_st_c,dd_st_n;
logic   [0:0]   dir_del;
logic   [2:0]   dd_pri;
logic   [2:0]   cur_pri;
logic   [0:0]   dd_eop;
logic   [31:0]  dd_data;
logic   [0:0]   dd_vld;
logic   [0:0]   flush_fifo;
//------------------------------------------------------------------------------------------//


//------------------------------------------------------------------------------------------//
//sram_cfg
//assign  sram_table[0]   =   5'b1_0000;
assign  sram_table[0]   =   {1'b1,FIX_SRAM_ADDR};
assign  sram_active_0   =   sram_table[0][4];
assign  sram_active_1   =   sram_table[1][4];
assign  sram_active_2   =   sram_table[2][4];
assign  sram_active_3   =   sram_table[3][4];
assign  sram_full_0     =   {s_cac_7.FULL[0],
                             s_cac_6.FULL[0],
                             s_cac_5.FULL[0],
                             s_cac_4.FULL[0],
                             s_cac_3.FULL[0],
                             s_cac_2.FULL[0],
                             s_cac_1.FULL[0],
                             s_cac_0.FULL[0]};
assign  sram_full_1     =   {s_cac_7.FULL[1],
                             s_cac_6.FULL[1],
                             s_cac_5.FULL[1],
                             s_cac_4.FULL[1],
                             s_cac_3.FULL[1],
                             s_cac_2.FULL[1],
                             s_cac_1.FULL[1],
                             s_cac_0.FULL[1]};
assign  sram_full_2     =   {s_cac_7.FULL[2],
                             s_cac_6.FULL[2],
                             s_cac_5.FULL[2],
                             s_cac_4.FULL[2],
                             s_cac_3.FULL[2],
                             s_cac_2.FULL[2],
                             s_cac_1.FULL[2],
                             s_cac_0.FULL[2]};
assign  sram_full_3     =   {s_cac_7.FULL[3],
                             s_cac_6.FULL[3],
                             s_cac_5.FULL[3],
                             s_cac_4.FULL[3],
                             s_cac_3.FULL[3],
                             s_cac_2.FULL[3],
                             s_cac_1.FULL[3],
                             s_cac_0.FULL[3]};
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        sram_active_0_r <= '0;
        sram_active_1_r <= '0;
        sram_active_2_r <= '0;
        sram_active_3_r <= '0;
    end
    else begin
        sram_active_0_r <=  sram_active_0;
        sram_active_1_r <=  sram_active_1;
        sram_active_2_r <=  sram_active_2;
        sram_active_3_r <=  sram_active_3;
    end
end 
//sram_empty
assign  cc_s.EMPTY[0]   =   &s_cac_0.EMPTY;
assign  cc_s.EMPTY[1]   =   &s_cac_1.EMPTY;
assign  cc_s.EMPTY[2]   =   &s_cac_2.EMPTY;
assign  cc_s.EMPTY[3]   =   &s_cac_3.EMPTY;
assign  cc_s.EMPTY[4]   =   &s_cac_4.EMPTY;
assign  cc_s.EMPTY[5]   =   &s_cac_5.EMPTY;
assign  cc_s.EMPTY[6]   =   &s_cac_6.EMPTY;
assign  cc_s.EMPTY[7]   =   &s_cac_7.EMPTY;

assign  cc_s.FULL[0]   =   &s_cac_0.FULL;
assign  cc_s.FULL[1]   =   &s_cac_1.FULL;
assign  cc_s.FULL[2]   =   &s_cac_2.FULL;
assign  cc_s.FULL[3]   =   &s_cac_3.FULL;
assign  cc_s.FULL[4]   =   &s_cac_4.FULL;
assign  cc_s.FULL[5]   =   &s_cac_5.FULL;
assign  cc_s.FULL[6]   =   &s_cac_6.FULL;
assign  cc_s.FULL[7]   =   &s_cac_7.FULL;

assign  sram_empty_1    =   s_cac_0.EMPTY[1]&&
                            s_cac_1.EMPTY[1]&&
                            s_cac_2.EMPTY[1]&&
                            s_cac_3.EMPTY[1]&&
                            s_cac_4.EMPTY[1]&&
                            s_cac_5.EMPTY[1]&&
                            s_cac_6.EMPTY[1]&&
                            s_cac_7.EMPTY[1];
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        sram_empty_1_r    <=  1'b1;
    end
    else if(sram_active_1)
        sram_empty_1_r    <=  sram_empty_1;
end 
assign  sram_empty_2    =   s_cac_0.EMPTY[2]&&
                            s_cac_1.EMPTY[2]&&
                            s_cac_2.EMPTY[2]&&
                            s_cac_3.EMPTY[2]&&
                            s_cac_4.EMPTY[2]&&
                            s_cac_5.EMPTY[2]&&
                            s_cac_6.EMPTY[2]&&
                            s_cac_7.EMPTY[2];
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        sram_empty_2_r    <=  1'b1;
    end
    else if(sram_active_2)
        sram_empty_2_r    <=  sram_empty_2;
end 
assign  sram_empty_3    =   s_cac_0.EMPTY[3]&&
                            s_cac_1.EMPTY[3]&&
                            s_cac_2.EMPTY[3]&&
                            s_cac_3.EMPTY[3]&&
                            s_cac_4.EMPTY[3]&&
                            s_cac_5.EMPTY[3]&&
                            s_cac_6.EMPTY[3]&&
                            s_cac_7.EMPTY[3];
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        sram_empty_3_r    <=  1'b1;
    end
    else if(sram_active_3)
        sram_empty_3_r    <=  sram_empty_3;
end 
//internel sram cfg
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        sram_table[1]   <=  '0;
    end
    else if(cc_s.SRAM_SHARE_VLD&&!sram_active_1)begin
        sram_table[1][4]    <=  1'b1;
        sram_table[1][3:0]  <=  cc_s.SRAM_SHARE;
    end
    else if(sram_active_1_r&&sram_empty_1)begin//need cac to low empty in share next cycle.
        sram_table[1][4]    <=  1'b0;
    end
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        sram_table[2]   <= '0;
    end
    else if(cc_s.SRAM_SHARE_VLD&&sram_active_1)begin
        sram_table[2][4]    <=  1'b1;
        sram_table[2][3:0]  <=  cc_s.SRAM_SHARE;
    end
    else if(sram_active_2_r&&sram_empty_2)begin
        sram_table[2][4]    <= '0;
    end
end 
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        sram_table[3]   <= '0;
    end
    else if(cc_s.SRAM_SHARE_VLD&&sram_active_1&&sram_active_2)begin
        sram_table[3][4]    <=  1'b1;
        sram_table[3][3:0]  <=  cc_s.SRAM_SHARE;
    end
    else if(sram_active_3_r&&sram_empty_3)begin
        sram_table[3][4]    <= '0;
    end
end
//release sram
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        cc_s.SRAM_RELEASE_VLD       <= '0;
        cc_s.SRAM_RELEASE           <= '0;
        s_cac_0.SRAM_RELEASE_VLD    <= '0;
        s_cac_0.SRAM_RELEASE        <= '0;
        s_cac_1.SRAM_RELEASE_VLD    <= '0;
        s_cac_1.SRAM_RELEASE        <= '0;
        s_cac_2.SRAM_RELEASE_VLD    <= '0;
        s_cac_2.SRAM_RELEASE        <= '0;
        s_cac_3.SRAM_RELEASE_VLD    <= '0;
        s_cac_3.SRAM_RELEASE        <= '0;
        s_cac_4.SRAM_RELEASE_VLD    <= '0;
        s_cac_4.SRAM_RELEASE        <= '0;
        s_cac_5.SRAM_RELEASE_VLD    <= '0;
        s_cac_5.SRAM_RELEASE        <= '0;
        s_cac_6.SRAM_RELEASE_VLD    <= '0;
        s_cac_6.SRAM_RELEASE        <= '0;
        s_cac_7.SRAM_RELEASE_VLD    <= '0;
        s_cac_7.SRAM_RELEASE        <= '0;
    end
    else if(sram_empty_1_r&&sram_active_1_r)begin
        cc_s.SRAM_RELEASE           <=  sram_table[1][3:0];
        cc_s.SRAM_RELEASE_VLD       <= 1'b1;
        s_cac_0.SRAM_RELEASE_VLD    <= 1'b1;
        s_cac_0.SRAM_RELEASE        <= sram_table[1][3:0];
        s_cac_1.SRAM_RELEASE_VLD    <= 1'b1;
        s_cac_1.SRAM_RELEASE        <= sram_table[1][3:0];
        s_cac_2.SRAM_RELEASE_VLD    <= 1'b1;
        s_cac_2.SRAM_RELEASE        <= sram_table[1][3:0];
        s_cac_3.SRAM_RELEASE_VLD    <= 1'b1;
        s_cac_3.SRAM_RELEASE        <= sram_table[1][3:0];
        s_cac_4.SRAM_RELEASE_VLD    <= 1'b1;
        s_cac_4.SRAM_RELEASE        <= sram_table[1][3:0];
        s_cac_5.SRAM_RELEASE_VLD    <= 1'b1;
        s_cac_5.SRAM_RELEASE        <= sram_table[1][3:0];
        s_cac_6.SRAM_RELEASE_VLD    <= 1'b1;
        s_cac_6.SRAM_RELEASE        <= sram_table[1][3:0];
        s_cac_7.SRAM_RELEASE_VLD    <= 1'b1;
        s_cac_7.SRAM_RELEASE        <= sram_table[1][3:0];
    end
    else if(sram_empty_2_r&&sram_active_2_r)begin
        cc_s.SRAM_RELEASE      <=  sram_table[2][3:0];
        cc_s.SRAM_RELEASE_VLD  <= 1'b1;
        s_cac_0.SRAM_RELEASE_VLD    <= 1'b1;
        s_cac_0.SRAM_RELEASE        <= sram_table[2][3:0];
        s_cac_1.SRAM_RELEASE_VLD    <= 1'b1;
        s_cac_1.SRAM_RELEASE        <= sram_table[2][3:0];
        s_cac_2.SRAM_RELEASE_VLD    <= 1'b1;
        s_cac_2.SRAM_RELEASE        <= sram_table[2][3:0];
        s_cac_3.SRAM_RELEASE_VLD    <= 1'b1;
        s_cac_3.SRAM_RELEASE        <= sram_table[2][3:0];
        s_cac_4.SRAM_RELEASE_VLD    <= 1'b1;
        s_cac_4.SRAM_RELEASE        <= sram_table[2][3:0];
        s_cac_5.SRAM_RELEASE_VLD    <= 1'b1;
        s_cac_5.SRAM_RELEASE        <= sram_table[2][3:0];
        s_cac_6.SRAM_RELEASE_VLD    <= 1'b1;
        s_cac_6.SRAM_RELEASE        <= sram_table[2][3:0];
        s_cac_7.SRAM_RELEASE_VLD    <= 1'b1;
        s_cac_7.SRAM_RELEASE        <= sram_table[2][3:0];
    end
    else if(sram_empty_3_r&&sram_active_3_r)begin
        cc_s.SRAM_RELEASE      <=  sram_table[3][3:0];
        cc_s.SRAM_RELEASE_VLD  <= 1'b1;
        s_cac_0.SRAM_RELEASE_VLD    <= 1'b1;
        s_cac_0.SRAM_RELEASE        <= sram_table[3][3:0];
        s_cac_1.SRAM_RELEASE_VLD    <= 1'b1;
        s_cac_1.SRAM_RELEASE        <= sram_table[3][3:0];
        s_cac_2.SRAM_RELEASE_VLD    <= 1'b1;
        s_cac_2.SRAM_RELEASE        <= sram_table[3][3:0];
        s_cac_3.SRAM_RELEASE_VLD    <= 1'b1;
        s_cac_3.SRAM_RELEASE        <= sram_table[3][3:0];
        s_cac_4.SRAM_RELEASE_VLD    <= 1'b1;
        s_cac_4.SRAM_RELEASE        <= sram_table[3][3:0];
        s_cac_5.SRAM_RELEASE_VLD    <= 1'b1;
        s_cac_5.SRAM_RELEASE        <= sram_table[3][3:0];
        s_cac_6.SRAM_RELEASE_VLD    <= 1'b1;
        s_cac_6.SRAM_RELEASE        <= sram_table[3][3:0];
        s_cac_7.SRAM_RELEASE_VLD    <= 1'b1;
        s_cac_7.SRAM_RELEASE        <= sram_table[3][3:0];
    end
    else begin
        cc_s.SRAM_RELEASE_VLD       <= '0;
        s_cac_0.SRAM_RELEASE_VLD    <= '0;
        s_cac_1.SRAM_RELEASE_VLD    <= '0;
        s_cac_2.SRAM_RELEASE_VLD    <= '0;
        s_cac_3.SRAM_RELEASE_VLD    <= '0;
        s_cac_4.SRAM_RELEASE_VLD    <= '0;
        s_cac_5.SRAM_RELEASE_VLD    <= '0;
        s_cac_6.SRAM_RELEASE_VLD    <= '0;
        s_cac_7.SRAM_RELEASE_VLD    <= '0;
    end
end 


assign  s_cac_0.SRAM_VLD      =   cc_s.SRAM_SHARE_VLD;
assign  s_cac_1.SRAM_VLD      =   cc_s.SRAM_SHARE_VLD;
assign  s_cac_2.SRAM_VLD      =   cc_s.SRAM_SHARE_VLD;
assign  s_cac_3.SRAM_VLD      =   cc_s.SRAM_SHARE_VLD;
assign  s_cac_4.SRAM_VLD      =   cc_s.SRAM_SHARE_VLD;
assign  s_cac_5.SRAM_VLD      =   cc_s.SRAM_SHARE_VLD;
assign  s_cac_6.SRAM_VLD      =   cc_s.SRAM_SHARE_VLD;
assign  s_cac_7.SRAM_VLD      =   cc_s.SRAM_SHARE_VLD;
assign  s_cac_0.SRAM_SHARE    =   cc_s.SRAM_SHARE;
assign  s_cac_1.SRAM_SHARE    =   cc_s.SRAM_SHARE;
assign  s_cac_2.SRAM_SHARE    =   cc_s.SRAM_SHARE;
assign  s_cac_3.SRAM_SHARE    =   cc_s.SRAM_SHARE;
assign  s_cac_4.SRAM_SHARE    =   cc_s.SRAM_SHARE;
assign  s_cac_5.SRAM_SHARE    =   cc_s.SRAM_SHARE;
assign  s_cac_6.SRAM_SHARE    =   cc_s.SRAM_SHARE;
assign  s_cac_7.SRAM_SHARE    =   cc_s.SRAM_SHARE;
//------------------------------------------------------------------------------------------//

//------------------------------------------------------------------------------------------//
//cache_logic
assign cache_en[0]  =   sram_active_0_r &&  (cc_s.DATA_STATUS0) && (cc_s.WR_SOP0)&&cache_en_pre[0];/////
assign cache_en[1]  =   sram_active_1_r &&  (cc_s.DATA_STATUS1) && (cc_s.WR_SOP1)&&cache_en_pre[1];////
assign cache_en[2]  =   sram_active_2_r &&  (cc_s.DATA_STATUS2) && (cc_s.WR_SOP2)&&cache_en_pre[2];///
assign cache_en[3]  =   sram_active_3_r &&  (cc_s.DATA_STATUS3) && (cc_s.WR_SOP3)&&cache_en_pre[3];/////
//------------------------------------------------------------------------------------------//

//------------------------------------------------------------------------------------------//
//get_addr_logic need four fifo to store data to get addr
//back cc vld next cycle to get addr from cac
//To output corret  vld , this needs 4 stages pipeline!!!!. pipe has bug!!change to fsm!!!
//assign  st_vld_data =   {sram_full_3,sram_full_2,sram_full_1,sram_full_0};
//st_vld_data is sram can write.
assign  st_vld_data[7:0]      =   ({7{(sram_cache_c_0 == IDLE)}} | ~(sram_full_0))&{7{sram_active_0_r}};
assign  st_vld_data[15:8]     =   ({7{(sram_cache_c_1 == IDLE)}} | ~(sram_full_1))&{7{sram_active_1_r}};
assign  st_vld_data[23:16]    =   ({7{(sram_cache_c_2 == IDLE)}} | ~(sram_full_2))&{7{sram_active_2_r}};
assign  st_vld_data[31:24]    =   ({7{(sram_cache_c_3 == IDLE)}} | ~(sram_full_3))&{7{sram_active_3_r}};
//rv_fsm
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        rv_fsm_c    <= RVIDLE;
    end
    else begin
        rv_fsm_c    <=  rv_fsm_n;
    end
end 
logic   [31:0]  st_vld_data_r;
logic   [3:0]   cc_port_0_r;
logic   [3:0]   cc_port_1_r;
logic   [3:0]   cc_port_2_r;
logic   [3:0]   cc_port_3_r;
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        st_vld_data_r   <=  '0;
        cc_port_0_r     <=  '0;
        cc_port_1_r     <=  '0;
        cc_port_2_r     <=  '0;
        cc_port_3_r     <=  '0;
    end
    else begin
        st_vld_data_r   <=  cc_s.ST_VLD_DATA;
        cc_port_0_r     <=  cc_port_0;
        cc_port_1_r     <=  cc_port_1;
        cc_port_2_r     <=  cc_port_2;
        cc_port_3_r     <=  cc_port_3;
    end
        
end 
//always_comb begin
//    rv_fsm_n    = rv_fsm_c;
//    cc_req      = '0;
//    cc_s.ST_VLD_DATA =  st_vld_data_r;
//    unique case (rv_fsm_c)
//        RVIDLE:begin
//            if(cc_s.ST_REQ)begin 
//                rv_fsm_n    =  FIX;
//                cc_req      = cc_s.ST_REQ_DATA[7:0];
//                cc_s.ST_VLD_DATA = '0;
//            end
//            else begin
//                rv_fsm_n    = RVIDLE;
//                cc_s.ST_VLD_DATA = '0;
//            end
//        end
//        FIX:begin
//            rv_fsm_n            = SHARE_1;
//            cc_req              = cc_req_data_r[15:8];
//            cc_s.ST_VLD_DATA[7:0]    = st_vld;
//            cc_port_0         = port;
//        end
//        SHARE_1:begin
//            rv_fsm_n            = SHARE_2;
//            cc_req              = cc_req_data_r[23:16];
//            cc_s.ST_VLD_DATA[15:8]   = st_vld;
//            cc_port_1         = port;
//        end
//        SHARE_2:begin
//            rv_fsm_n            = RVIDLE;
//            cc_req              = cc_req_data_r[31:24];
//            cc_s.ST_VLD_DATA[23:16]  = st_vld;
//            cc_port_2         = port;
//        end
//        SHARE_3:begin
//            rv_fsm_n            = RVIDLE;
//            cc_req              = '0;
//            cc_s.ST_VLD_DATA[31:24]  = st_vld;
//            cc_port_3         = port;
//        end
//        default:begin 
//        rv_fsm_n = RVIDLE;
//        cc_req   = '0;
//        cc_s.ST_VLD_DATA= '0;   
//        end
//    endcase
//end
always_comb begin
    rv_fsm_n    = rv_fsm_c;
    cc_req      = '0;
    cc_s.ST_VLD_DATA =  st_vld_data_r;
    cc_port_0   =   cc_port_0_r;
    cc_port_1   =   cc_port_1_r;
    cc_port_2   =   cc_port_2_r;
    cc_port_3   =   cc_port_3_r;
    unique case (rv_fsm_c)
        RVIDLE:begin
            if(cc_s.ST_REQ)begin 
                rv_fsm_n    =  FIX;
                cc_req      = cc_s.ST_REQ_DATA[7:0];
                cc_s.ST_VLD_DATA = '0;
            end
            else begin
                rv_fsm_n    = RVIDLE;
                cc_req      = '0;
                cc_s.ST_VLD_DATA = '0;
            end
        end
        FIX:begin
            rv_fsm_n            = SHARE_1;
            cc_req              = cc_req_data_r[15:8];
            cc_s.ST_VLD_DATA[7:0]    = st_vld;
            cc_port_0         = port;
        end
        SHARE_1:begin
            rv_fsm_n            = SHARE_2;
            cc_req              = cc_req_data_r[23:16];
            cc_s.ST_VLD_DATA[15:8]   = st_vld;
            cc_port_1         = port;
        end
        SHARE_2:begin
            rv_fsm_n            = RVIDLE;
            cc_req              = cc_req_data_r[31:24];
            cc_s.ST_VLD_DATA[23:16]  = st_vld;
            cc_port_2         = port;
        end
        SHARE_3:begin
            rv_fsm_n            = RVIDLE;
            cc_req              = '0;
            cc_s.ST_VLD_DATA[31:24]  = st_vld;
            cc_port_3         = port;
        end
        default:begin 
        rv_fsm_n = RVIDLE;
        cc_req   = '0;
        cc_s.ST_VLD_DATA= '0;   
        end
    endcase
end
assign  cc_s.ST_VLD =   rv_fsm_c == SHARE_3;
//stage_1 : if can store in fix_sram
always_ff @(posedge CLK or negedge RST_N) begin
    if (!RST_N)begin
        st_vld       <=  '0;
        cache_en_pre <= '0;
        port         <= '0;
    end
    else if((|(cc_req & st_vld_data[7:0])) && !cache_en_pre[0])begin
        st_vld              <=  cc_req;
        cache_en_pre[0]         <=  1'b1;
        port                <=  2'b00;
    end
    else if((|(cc_req & st_vld_data[15:8])) && !cache_en_pre[1])begin
        st_vld              <=  cc_req;
        cache_en_pre[1]         <=  1'b1;
        port                <=  2'b01;
    end
    else if((|(cc_req & st_vld_data[23:16]))&& !cache_en_pre[2])begin
        st_vld              <=  cc_req;
        cache_en_pre[2]         <=  1'b1;
        port                <=  2'b10;
    end
    else if((|(cc_req & st_vld_data[31:24]))&& !cache_en_pre[3])begin
        st_vld              <=   cc_req;
        cache_en_pre[3]         <=  1'b1;
        port                <=  2'b11;
    end
    else if(((rv_fsm_c == RVIDLE) && cc_s.WR_SOP0 &&
        (!cc_s.DATA_STATUS0)&&cache_en_pre[0]) ||
        wa_s_0.EOP)
        cache_en_pre[0]    <= 1'b0;
    else if(((rv_fsm_c == RVIDLE) && cc_s.WR_SOP1 &&
        (!cc_s.DATA_STATUS1)&&cache_en_pre[1]) ||
        wa_s_1.EOP)
        cache_en_pre[1]    <= 1'b0;
    else if(((rv_fsm_c == RVIDLE) && cc_s.WR_SOP2 &&
        (!cc_s.DATA_STATUS2)&&cache_en_pre[2]) ||
        wa_s_2.EOP)
        cache_en_pre[2]    <= 1'b0;
    else if(((rv_fsm_c == RVIDLE) && cc_s.WR_SOP3 &&
        (!cc_s.DATA_STATUS3)&&cache_en_pre[3]) ||
        wa_s_3.EOP)
        cache_en_pre[3]    <= 1'b0;
    else begin
        st_vld              <=  '0;
        port                <=  2'b00;
    end
end 
//cache_en_pre logic turn low logic don't have :if pre cache but dd ,cache_en_pre ->0
//one poket done cache_en_pre ->0
//always_ff @(posedge CLK ) begin
//    if(((rv_fsm_c == RVIDLE) && cc_s.WR_SOP0 &&
//        (!cc_s.DATA_STATUS0)&&cache_en_pre[0]) ||
//        wa_s_0.EOP)
//        cache_en_pre[0]    <= 1'b0;
//end 
//always_ff @(posedge CLK ) begin
//    if(((rv_fsm_c == RVIDLE) && cc_s.WR_SOP1 &&
//        (!cc_s.DATA_STATUS1)&&cache_en_pre[1]) ||
//        wa_s_1.EOP)
//        cache_en_pre[1]    <= 1'b0;
//end 
//always_ff @(posedge CLK ) begin
//    if(((rv_fsm_c == RVIDLE) && cc_s.WR_SOP2 &&
//        (!cc_s.DATA_STATUS2)&&cache_en_pre[2]) ||
//        wa_s_2.EOP)
//        cache_en_pre[2]    <= 1'b0;
//end 
//always_ff @(posedge CLK ) begin
//    if(((rv_fsm_c == RVIDLE) && cc_s.WR_SOP3 &&
//        (!cc_s.DATA_STATUS3)&&cache_en_pre[3]) ||
//        wa_s_3.EOP)
//        cache_en_pre[3]    <= 1'b0;
//end 
//always_ff @(posedge CLK or negedge RST_N) begin
//    if(!RST_N)begin
//        st_vld_data_1_r      <=  '0;
//        st_vld_data_1_2r     <=  '0;
//        st_vld_data_1_3r     <=  '0;
//    end
//    else begin
//        st_vld_data_1_r      <=  st_vld_data_1;
//        st_vld_data_1_2r     <=  st_vld_data_1_r;
//        st_vld_data_1_3r     <=  st_vld_data_1_2r;
//    end
//end 
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        cc_req_data_r    <= '0;
    end
    else if (cc_s.ST_REQ)begin
        cc_req_data_r   <=  cc_s.ST_REQ_DATA;
    end
end 

//------------------------------------------------------------------------------------------//

//------------------------------------------------------------------------------------------//
//cache_fsm
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
    sram_cache_c_0  <=  IDLE;
    end
    else begin
    sram_cache_c_0  <=  sram_cache_n_0;
    end
end 

always_comb begin
    sram_cache_n_0  =   sram_cache_c_0;
    unique case(sram_cache_c_0)
        IDLE:begin
            if(sram_active_0_r&&cache_en[0])  
                sram_cache_n_0  =   GET_ADDR;
            else
                sram_cache_n_0  =   IDLE;
        end
        GET_ADDR:begin
            if(get_addr_0)
                sram_cache_n_0  =   TRAN_ADDR;
            else
                sram_cache_n_0  =   GET_ADDR;
        end
        TRAN_ADDR:begin
            if(tran_addr_done_0)
                sram_cache_n_0  =   TRAN_DATA;
            else
                sram_cache_n_0  =   TRAN_ADDR;
        end
        TRAN_DATA:begin
            if(wa_s_0.EOP)
                sram_cache_n_0  =   IDLE;
            else
                sram_cache_n_0  =   TRAN_DATA;
        end
        default:sram_cache_n_0  =   IDLE;
    endcase
end 

always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
    sram_cache_c_1  <=  IDLE;
    end
    else begin
    sram_cache_c_1  <=  sram_cache_n_1;
    end
end 

always_comb begin
    sram_cache_n_1  =   sram_cache_c_1;
    unique case(sram_cache_c_1)
        IDLE:begin
            if(sram_active_1_r&&cache_en[1])  
                sram_cache_n_1  =   GET_ADDR;
            else
                sram_cache_n_1  =   IDLE;
        end
        GET_ADDR:begin
            if(get_addr_1)
                sram_cache_n_1  =   TRAN_ADDR;
            else
                sram_cache_n_1  =   GET_ADDR;
        end
        TRAN_ADDR:begin
            if(tran_addr_done_1)
                sram_cache_n_1  =   TRAN_DATA;
            else
                sram_cache_n_1  =   TRAN_ADDR;
        end
        TRAN_DATA:begin
            if(wa_s_1.EOP)
                sram_cache_n_1  =   IDLE;
            else
                sram_cache_n_1  =   TRAN_DATA;
        end
        default:sram_cache_n_1  =   IDLE;
    endcase
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
    sram_cache_c_2  <=  IDLE;
    end
    else begin
    sram_cache_c_2  <=  sram_cache_n_2;
    end
end 

always_comb begin
    sram_cache_n_2  =   sram_cache_c_2;
    unique case(sram_cache_c_2)
        IDLE:begin
            if(sram_active_2_r&&cache_en[2])  
                sram_cache_n_2  =   GET_ADDR;
            else
                sram_cache_n_2  =   IDLE;
        end
        GET_ADDR:begin
            if(get_addr_2)
                sram_cache_n_2  =   TRAN_ADDR;
            else
                sram_cache_n_2  =   GET_ADDR;
        end
        TRAN_ADDR:begin
            if(tran_addr_done_2)
                sram_cache_n_2  =   TRAN_DATA;
            else
                sram_cache_n_2  =   TRAN_ADDR;
        end
        TRAN_DATA:begin
            if(wa_s_2.EOP)
                sram_cache_n_2  =   IDLE;
            else
                sram_cache_n_2  =   TRAN_DATA;
        end
        default:sram_cache_n_2  =   IDLE;
    endcase
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
    sram_cache_c_3  <=  IDLE;
    end
    else begin
    sram_cache_c_3  <=  sram_cache_n_3;
    end
end 

always_comb begin
    sram_cache_n_3  =   sram_cache_c_3;
    unique case(sram_cache_c_3)
        IDLE:begin
            if(sram_active_3_r&&cache_en[3])  
                sram_cache_n_3  =   GET_ADDR;
            else
                sram_cache_n_3  =   IDLE;
        end
        GET_ADDR:begin
            if(get_addr_3)
                sram_cache_n_3  =   TRAN_ADDR;
            else
                sram_cache_n_3  =   GET_ADDR;
        end
        TRAN_ADDR:begin
            if(tran_addr_done_3)
                sram_cache_n_3  =   TRAN_DATA;
            else
                sram_cache_n_3  =   TRAN_ADDR;
        end
        TRAN_DATA:begin
            if(wa_s_3.EOP)
                sram_cache_n_3  =   IDLE;
            else
                sram_cache_n_3  =   TRAN_DATA;
        end
        default:sram_cache_n_3  =   IDLE;
    endcase
end
//------------------------------------------------------------------------------------------//
//-----------------------------------------------------------------------------------------//
//store data because get addr need some Time so there are 4 fifo
logic   [0:0]   fifo_push_0;
logic   [35:0]  fifo_data_0;
logic   [0:0]   fifo_pop_0;
logic   [35:0]  tran_data_0;
logic   [0:0]   fifo_empty_0;
logic   [0:0]   fifo_push_1;
logic   [35:0]  fifo_data_1;
logic   [0:0]   fifo_pop_1;
logic   [35:0]  tran_data_1;
logic   [0:0]   fifo_empty_1;
logic   [0:0]   fifo_push_2;
logic   [35:0]  fifo_data_2;
logic   [0:0]   fifo_pop_2;
logic   [35:0]  tran_data_2;
logic   [0:0]   fifo_empty_2;
logic   [0:0]   fifo_push_3;
logic   [35:0]  fifo_data_3;
logic   [0:0]   fifo_pop_3;
logic   [35:0]  tran_data_3;
logic   [0:0]   fifo_empty_3;
// push logic

always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        fifo_push_0 <= '0;
        fifo_data_0 <= '0;
    end
    else begin
        case(2'b00)
            cc_port_0:begin
                if(cc_s.WR_VLD0)begin
                    fifo_push_0 <=  1'b1;
                    fifo_data_0 <=  cc_s.WR_DATA0;
                end
                else begin
                    fifo_push_0 <=  1'b0;
                end
            end
            cc_port_1:begin
                if(cc_s.WR_VLD1)begin
                    fifo_push_0 <=  1'b1;
                    fifo_data_0 <=  cc_s.WR_DATA1;
                end
                else begin
                    fifo_push_0 <=  1'b0;
                end
            end
            cc_port_2:begin
                if(cc_s.WR_VLD2)begin
                    fifo_push_0 <=  1'b1;
                    fifo_data_0 <=  cc_s.WR_DATA2;
                end
                else begin
                    fifo_push_0 <=  1'b0;
                end
            end
            cc_port_3:begin
                if(cc_s.WR_VLD3)begin
                    fifo_push_0 <=  1'b1;
                    fifo_data_0 <=  cc_s.WR_DATA3;
                end
                else begin
                    fifo_push_0 <=  1'b0;
                end
            end
        endcase
    end
end 
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        fifo_push_1 <= '0;
        fifo_data_1 <= '0;
    end
    else begin
        case(2'b01)
            cc_port_0:begin
                if(cc_s.WR_VLD0)begin
                    fifo_push_1 <=  1'b1;
                    fifo_data_1 <=  cc_s.WR_DATA0;
                end
                else begin
                    fifo_push_1 <=  1'b0;
                end
            end
            cc_port_1:begin
                if(cc_s.WR_VLD1)begin
                    fifo_push_1 <=  1'b1;
                    fifo_data_1 <=  cc_s.WR_DATA1;
                end
                else begin
                    fifo_push_1 <=  1'b0;
                end
            end
            cc_port_2:begin
                if(cc_s.WR_VLD2)begin
                    fifo_push_1 <=  1'b1;
                    fifo_data_1 <=  cc_s.WR_DATA2;
                end
                else begin
                    fifo_push_1 <=  1'b0;
                end
            end
            cc_port_3:begin
                if(cc_s.WR_VLD3)begin
                    fifo_push_1 <=  1'b1;
                    fifo_data_1 <=  cc_s.WR_DATA3;
                end
                else begin
                    fifo_push_1 <=  1'b0;
                end
            end
        endcase
    end
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        fifo_push_2 <= '0;
        fifo_data_2 <= '0;
    end
    else begin
        case(2'b10)
            cc_port_0:begin
                if(cc_s.WR_VLD0)begin
                    fifo_push_2 <=  1'b1;
                    fifo_data_2 <=  cc_s.WR_DATA0;
                end
                else begin
                    fifo_push_2 <=  1'b0;
                end
            end
            cc_port_1:begin
                if(cc_s.WR_VLD1)begin
                    fifo_push_2 <=  1'b1;
                    fifo_data_2 <=  cc_s.WR_DATA1;
                end
                else begin
                    fifo_push_2 <=  1'b0;
                end
            end
            cc_port_2:begin
                if(cc_s.WR_VLD2)begin
                    fifo_push_2 <=  1'b1;
                    fifo_data_2 <=  cc_s.WR_DATA2;
                end
                else begin
                    fifo_push_2 <=  1'b0;
                end
            end
            cc_port_3:begin
                if(cc_s.WR_VLD3)begin
                    fifo_push_2 <=  1'b1;
                    fifo_data_2 <=  cc_s.WR_DATA3;
                end
                else begin
                    fifo_push_2 <=  1'b0;
                end
            end
        endcase
    end
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        fifo_push_3 <= '0;
        fifo_data_3 <= '0;
    end
    else begin
        case(2'b11)
            cc_port_0:begin
                if(cc_s.WR_VLD0)begin
                    fifo_push_3 <=  1'b1;
                    fifo_data_3 <=  cc_s.WR_DATA0;
                end
                else begin
                    fifo_push_3 <=  1'b0;
                end
            end
            cc_port_1:begin
                if(cc_s.WR_VLD1)begin
                    fifo_push_3 <=  1'b1;
                    fifo_data_3 <=  cc_s.WR_DATA1;
                end
                else begin
                    fifo_push_3 <=  1'b0;
                end
            end
            cc_port_2:begin
                if(cc_s.WR_VLD2)begin
                    fifo_push_3 <=  1'b1;
                    fifo_data_3 <=  cc_s.WR_DATA2;
                end
                else begin
                    fifo_push_3 <=  1'b0;
                end
            end
            cc_port_3:begin
                if(cc_s.WR_VLD3)begin
                    fifo_push_3 <=  1'b1;
                    fifo_data_3 <=  cc_s.WR_DATA3;
                end
                else begin
                    fifo_push_3 <=  1'b0;
                end
            end
        endcase
    end
end

//pop logic
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        fifo_pop_0  <= 1'b0;
    end
    else if(sram_cache_c_0==TRAN_DATA && !fifo_empty_0)
        fifo_pop_0  <= 1'b1;
    else
        fifo_pop_0  <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        fifo_pop_1  <= 1'b0;
    end
    else if(sram_cache_c_1==TRAN_DATA && !fifo_empty_1)
        fifo_pop_1  <= 1'b1;
    else
        fifo_pop_1  <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        fifo_pop_2  <= 1'b0;
    end
    else if(sram_cache_c_2==TRAN_DATA && !fifo_empty_2)
        fifo_pop_2  <= 1'b1;
    else
        fifo_pop_2  <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        fifo_pop_3  <= 1'b0;
    end
    else if(sram_cache_c_3==TRAN_DATA && !fifo_empty_3)
        fifo_pop_3  <= 1'b1;
    else
        fifo_pop_3  <= '0;
end




//pop logic
sync_fifo#(.FIFO_WIDTH(36),
           .FIFO_DEPTH(8))
           U0(.CLK(CLK),
              .RST_N(RST_N),
              .WR_EN(fifo_push_0),
              .WR_DATA(fifo_data_0),
              .RD_EN(fifo_pop_0),
              .CLEAR(0),
              .FLUSH(0),
              .RD_DATA(tran_data_0),
              .FULL(),
              .EMPTY(fifo_empty_0)
              );
sync_fifo#(.FIFO_WIDTH(36),
           .FIFO_DEPTH(8))
           U1(.CLK(CLK),
              .RST_N(RST_N),
              .WR_EN(fifo_push_1),
              .WR_DATA(fifo_data_1),
              .RD_EN(fifo_pop_1),
              .CLEAR(0),
              .FLUSH(0),
              .RD_DATA(tran_data_1),
              .FULL(),
              .EMPTY(fifo_empty_1)
              );
sync_fifo#(.FIFO_WIDTH(36),
           .FIFO_DEPTH(8))
           U2(.CLK(CLK),
              .RST_N(RST_N),
              .WR_EN(fifo_push_2),
              .WR_DATA(fifo_data_2),
              .RD_EN(fifo_pop_2),
              .CLEAR(0),
              .FLUSH(0),
              .RD_DATA(tran_data_2),
              .FULL(),
              .EMPTY(fifo_empty_2)
           );
sync_fifo#(.FIFO_WIDTH(36),
           .FIFO_DEPTH(8))
           U3(.CLK(CLK),
              .RST_N(RST_N),
              .WR_EN(fifo_push_3),
              .WR_DATA(fifo_data_3),
              .RD_EN(fifo_pop_3),
              .CLEAR(0),
              .FLUSH(0),
              .RD_DATA(tran_data_3),
              .FULL(),
              .EMPTY(fifo_empty_3)
              );
//------------------------------------------------------------------------------------------//
//get_addr_logic:pre_store data and get addr from cac
//fix_sram
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        fix_pri <= '0;
        fix_size<= '0;
    end
    else if (sram_cache_c_0==GET_ADDR)begin
        case(2'b00)
            cc_port_0:begin
                fix_pri <=  cc_s.DATA_PRI0;
                fix_size<=  cc_s.DATA_SIZE0;
            end
            cc_port_1:begin
                fix_pri <=  cc_s.DATA_PRI1;
                fix_size<=  cc_s.DATA_SIZE1;
            end
            cc_port_2:begin
                fix_pri <=  cc_s.DATA_PRI2;
                fix_size<=  cc_s.DATA_SIZE2;
            end
            cc_port_3:begin
                fix_pri <=  cc_s.DATA_PRI3;
                fix_size<=  cc_s.DATA_SIZE3;
            end
        endcase
    end
//    else if(sram_cache_c_0==IDLE)begin
//        fix_pri <=  '0;
//    end
end 
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s3_pri <= '0;
        s3_size<= '0;
    end
    else if (sram_cache_c_3==GET_ADDR)begin
        case(2'b11)
            cc_port_0:begin
                s3_pri <=  cc_s.DATA_PRI0;
                s3_size<=  cc_s.DATA_SIZE0;
            end
            cc_port_1:begin
                s3_pri <=  cc_s.DATA_PRI1;
                s3_size<=  cc_s.DATA_SIZE1;
            end
            cc_port_2:begin
                s3_pri <=  cc_s.DATA_PRI2;
                s3_size<=  cc_s.DATA_SIZE2;
            end
            cc_port_3:begin
                s3_pri <=  cc_s.DATA_PRI3;
                s3_size<=  cc_s.DATA_SIZE3;
            end
        endcase
    end
//    else if(sram_cache_c_0==IDLE)begin
//        s3_pri <=  '0;
//    end
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s1_pri <= '0;
        s1_size<= '0;
    end
    else if (sram_cache_c_1==GET_ADDR)begin
        case(2'b01)
            cc_port_0:begin
                s1_pri <=  cc_s.DATA_PRI0;
                s1_size<=  cc_s.DATA_SIZE0;
            end
            cc_port_1:begin
                s1_pri <=  cc_s.DATA_PRI1;
                s1_size<=  cc_s.DATA_SIZE1;
            end
            cc_port_2:begin
                s1_pri <=  cc_s.DATA_PRI2;
                s1_size<=  cc_s.DATA_SIZE2;
            end
            cc_port_3:begin
                s1_pri <=  cc_s.DATA_PRI3;
                s1_size<=  cc_s.DATA_SIZE3;
            end
        endcase
    end
//    else if(sram_cache_c_0==IDLE)begin
//        s2_pri <=  '0;
//    end
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s2_pri <= '0;
        s2_size<= '0;
    end
    else if (sram_cache_c_2==GET_ADDR)begin
        case(2'b10)
            cc_port_0:begin
                s2_pri <=  cc_s.DATA_PRI0;
                s2_size<=  cc_s.DATA_SIZE0;
            end
            cc_port_1:begin
                s2_pri <=  cc_s.DATA_PRI1;
                s2_size<=  cc_s.DATA_SIZE1;
            end
            cc_port_2:begin
                s2_pri <=  cc_s.DATA_PRI2;
                s2_size<=  cc_s.DATA_SIZE2;
            end
            cc_port_3:begin
                s2_pri <=  cc_s.DATA_PRI3;
                s2_size<=  cc_s.DATA_SIZE3;
            end
        endcase
    end
//    else if(sram_cache_c_0==IDLE)begin
//        s2_pri <=  '0;
//    end
end 
//always_ff @(posedge CLK or negedge RST_N) begin
//    if(RST_N)begin
//        s_cac_0.WR_REQ   <= '0;
//    end
//    else if(((cc_s.DATA_PRIO==0)&&cc_s.WR_SOP0)||
//            ((cc_s.DATA_PRI1==0)&&cc_s.WR_SOP1)||
//            ((cc_s.DATA_PRI2==0)&&cc_s.WR_SOP2)||
//            ((cc_s.DATA_PRI3==0)&&cc_s.WR_SOP3))begin
//        s_cac_0.WR_REQ   <= {(sram_cache_c_3==GET_ADDR),
//                             (sram_cache_c_2==GET_ADDR),
//                             (sram_cache_c_1==GET_ADDR),
//                             (sram_cache_c_0==GET_ADDR)   
//        };
//    end
//end 

//st send req to cac-------------------------------------------------
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_00.WR_REQ <= '0;
    end
    else if(fix_pri==3'b00&&(sram_cache_c_0==GET_ADDR))
        s_imc_00.WR_REQ <= 1'b1;
    else
        s_imc_00.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_01.WR_REQ <= '0;
    end
    else if(s1_pri==3'b00&&(sram_cache_c_1==GET_ADDR))
        s_imc_01.WR_REQ <= 1'b1;
    else
        s_imc_01.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_02.WR_REQ <= '0;
    end
    else if(s2_pri==3'b010&&(sram_cache_c_2==GET_ADDR))
        s_imc_02.WR_REQ <= 1'b1;
    else
        s_imc_02.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_03.WR_REQ <= '0;
    end
    else if(s3_pri==3'b011&&(sram_cache_c_3==GET_ADDR))
        s_imc_03.WR_REQ <= 1'b1;
    else
        s_imc_03.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_10.WR_REQ <= '0;
    end
    else if(fix_pri==3'b001&&(sram_cache_c_0==GET_ADDR))
        s_imc_10.WR_REQ <= 1'b1;
    else
        s_imc_10.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_11.WR_REQ <= '0;
    end
    else if(s1_pri==3'b001&&(sram_cache_c_1==GET_ADDR))
        s_imc_11.WR_REQ <= 1'b1;
    else
        s_imc_11.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_12.WR_REQ <= '0;
    end
    else if(s2_pri==3'b001&&(sram_cache_c_2==GET_ADDR))
        s_imc_12.WR_REQ <= 1'b1;
    else
        s_imc_12.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_13.WR_REQ <= '0;
    end
    else if(s3_pri==3'b001&&(sram_cache_c_3==GET_ADDR))
        s_imc_13.WR_REQ <= 1'b1;
    else
        s_imc_13.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_20.WR_REQ <= '0;
    end
    else if(fix_pri==3'b010&&(sram_cache_c_0==GET_ADDR))
        s_imc_20.WR_REQ <= 1'b1;
    else
        s_imc_20.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_21.WR_REQ <= '0;
    end
    else if(s1_pri==3'b010&&(sram_cache_c_1==GET_ADDR))
        s_imc_21.WR_REQ <= 1'b1;
    else
        s_imc_21.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_22.WR_REQ <= '0;
    end
    else if(s2_pri==3'b010&&(sram_cache_c_2==GET_ADDR))
        s_imc_22.WR_REQ <= 1'b1;
    else
        s_imc_22.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_23.WR_REQ <= '0;
    end
    else if(s3_pri==3'b010&&(sram_cache_c_3==GET_ADDR))
        s_imc_23.WR_REQ <= 1'b1;
    else
        s_imc_23.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_30.WR_REQ <= '0;
    end
    else if(fix_pri==3'b011&&(sram_cache_c_0==GET_ADDR))
        s_imc_30.WR_REQ <= 1'b1;
    else
        s_imc_30.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_31.WR_REQ <= '0;
    end
    else if(s1_pri==3'b011&&(sram_cache_c_1==GET_ADDR))
        s_imc_31.WR_REQ <= 1'b1;
    else
        s_imc_31.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_32.WR_REQ <= '0;
    end
    else if(s2_pri==3'b011&&(sram_cache_c_2==GET_ADDR))
        s_imc_32.WR_REQ <= 1'b1;
    else
        s_imc_32.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_33.WR_REQ <= '0;
    end
    else if(s3_pri==3'b011&&(sram_cache_c_3==GET_ADDR))
        s_imc_33.WR_REQ <= 1'b1;
    else
        s_imc_33.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_40.WR_REQ <= '0;
    end
    else if(fix_pri==3'b100&&(sram_cache_c_0==GET_ADDR))
        s_imc_40.WR_REQ <= 1'b1;
    else
        s_imc_40.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_41.WR_REQ <= '0;
    end
    else if(s1_pri==3'b100&&(sram_cache_c_1==GET_ADDR))
        s_imc_41.WR_REQ <= 1'b1;
    else
        s_imc_41.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_42.WR_REQ <= '0;
    end
    else if(s2_pri==3'b100&&(sram_cache_c_2==GET_ADDR))
        s_imc_42.WR_REQ <= 1'b1;
    else
        s_imc_42.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_43.WR_REQ <= '0;
    end
    else if(s3_pri==3'b100&&(sram_cache_c_3==GET_ADDR))
        s_imc_43.WR_REQ <= 1'b1;
    else
        s_imc_43.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_50.WR_REQ <= '0;
    end
    else if(fix_pri==3'b101&&(sram_cache_c_0==GET_ADDR))
        s_imc_50.WR_REQ <= 1'b1;
    else
        s_imc_50.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_51.WR_REQ <= '0;
    end
    else if(s1_pri==3'b101&&(sram_cache_c_1==GET_ADDR))
        s_imc_51.WR_REQ <= 1'b1;
    else
        s_imc_51.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_52.WR_REQ <= '0;
    end
    else if(s2_pri==3'b101&&(sram_cache_c_2==GET_ADDR))
        s_imc_52.WR_REQ <= 1'b1;
    else
        s_imc_52.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_53.WR_REQ <= '0;
    end
    else if(s3_pri==3'b101&&(sram_cache_c_3==GET_ADDR))
        s_imc_53.WR_REQ <= 1'b1;
    else
        s_imc_53.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_60.WR_REQ <= '0;
    end
    else if(fix_pri==3'b110&&(sram_cache_c_0==GET_ADDR))
        s_imc_60.WR_REQ <= 1'b1;
    else
        s_imc_60.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_61.WR_REQ <= '0;
    end
    else if(s1_pri==3'b110&&(sram_cache_c_1==GET_ADDR))
        s_imc_61.WR_REQ <= 1'b1;
    else
        s_imc_61.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_62.WR_REQ <= '0;
    end
    else if(s2_pri==3'b110&&(sram_cache_c_2==GET_ADDR))
        s_imc_62.WR_REQ <= 1'b1;
    else
        s_imc_62.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_63.WR_REQ <= '0;
    end
    else if(s3_pri==3'b110&&(sram_cache_c_3==GET_ADDR))
        s_imc_63.WR_REQ <= 1'b1;
    else
        s_imc_63.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_70.WR_REQ <= '0;
    end
    else if(fix_pri==3'b111&&(sram_cache_c_0==GET_ADDR))
        s_imc_70.WR_REQ <= 1'b1;
    else
        s_imc_70.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_71.WR_REQ <= '0;
    end
    else if(s1_pri==3'b111&&(sram_cache_c_1==GET_ADDR))
        s_imc_71.WR_REQ <= 1'b1;
    else
        s_imc_71.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_72.WR_REQ <= '0;
    end
    else if(s2_pri==3'b111&&(sram_cache_c_2==GET_ADDR))
        s_imc_72.WR_REQ <= 1'b1;
    else
        s_imc_72.WR_REQ <= '0;
end
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        s_imc_73.WR_REQ <= '0;
    end
    else if(s3_pri==3'b111&&(sram_cache_c_3==GET_ADDR))
        s_imc_73.WR_REQ <= 1'b1;
    else
        s_imc_73.WR_REQ <= '0;
end

//cac back vld to st-------------------------------------------------
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        get_addr_0 <= '0;
        fix_addr   <= '0;
    end
    else if(sram_cache_c_0==GET_ADDR)begin
        case(fix_pri)
            3'b000:begin
                get_addr_0  <= s_imc_00.WR_VLD;
                fix_addr    <= s_imc_00.WR_ADDR;                
            end
            3'b001:begin
                get_addr_0  <= s_imc_10.WR_VLD;
                fix_addr    <= s_imc_10.WR_ADDR; 
            end
            3'b010:begin
                get_addr_0  <= s_imc_20.WR_VLD;
                fix_addr    <= s_imc_20.WR_ADDR; 
            end
            3'b011:begin
                get_addr_0  <= s_imc_30.WR_VLD;
                fix_addr    <= s_imc_30.WR_ADDR; 
            end
            3'b100:begin
                get_addr_0  <= s_imc_40.WR_VLD;
                fix_addr    <= s_imc_40.WR_ADDR; 
            end
            3'b101:begin
                get_addr_0  <= s_imc_50.WR_VLD;
                fix_addr    <= s_imc_50.WR_ADDR; 
            end
            3'b110:begin
                get_addr_0  <= s_imc_60.WR_VLD;
                fix_addr    <= s_imc_60.WR_ADDR; 
            end
            3'b111:begin
                get_addr_0  <= s_imc_70.WR_VLD;
                fix_addr    <= s_imc_70.WR_ADDR; 
            end
        endcase
    end
    else begin
        get_addr_0  <=   '0;
        if(sram_cache_c_0==IDLE)begin
            fix_addr    <=   '0;
        end
        else
            fix_addr    <=   fix_addr;
    end
end 
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        get_addr_1 <= '0;
        s1_addr   <= '0;
    end
    else if(sram_cache_c_1==GET_ADDR)begin
        case(s1_pri)
            3'b000:begin
                get_addr_1  <= s_imc_01.WR_VLD;
                s1_addr     <= s_imc_01.WR_ADDR;
            end
            3'b001:begin
                get_addr_1  <= s_imc_11.WR_VLD;
                s1_addr     <= s_imc_11.WR_ADDR;
            end
            3'b010:begin
                get_addr_1  <= s_imc_21.WR_VLD;
                s1_addr     <= s_imc_21.WR_ADDR;
            end
            3'b011:begin
                get_addr_1  <= s_imc_31.WR_VLD;
                s1_addr     <= s_imc_31.WR_ADDR;
            end
            3'b100:begin
                get_addr_1  <= s_imc_41.WR_VLD;
                s1_addr     <= s_imc_41.WR_ADDR;
            end
            3'b101:begin
                get_addr_1  <= s_imc_51.WR_VLD;
                s1_addr     <= s_imc_51.WR_ADDR;
            end
            3'b110:begin
                get_addr_1  <= s_imc_61.WR_VLD;
                s1_addr     <= s_imc_61.WR_ADDR;
            end
            3'b111:begin
                get_addr_1  <= s_imc_71.WR_VLD;
                s1_addr     <= s_imc_71.WR_ADDR;
            end
        endcase
    end
    else begin
        get_addr_1  <=   '0;
        if(sram_cache_c_1==IDLE)begin
            s1_addr    <=   '0;
        end
        else
            s1_addr    <=   s1_addr;
    end
end 
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        get_addr_2 <= '0;
        s2_addr   <= '0;
    end
    else if(sram_cache_c_2==GET_ADDR)begin
        case(s2_pri)
            3'b000:begin
                get_addr_2  <= s_imc_02.WR_VLD;
                s2_addr     <= s_imc_02.WR_ADDR;
            end
            3'b001:begin
                get_addr_2  <= s_imc_12.WR_VLD;
                s2_addr     <= s_imc_12.WR_ADDR;
            end
            3'b010:begin
                get_addr_2  <= s_imc_22.WR_VLD;
                s2_addr     <= s_imc_22.WR_ADDR;
            end
            3'b011:begin
                get_addr_2  <= s_imc_32.WR_VLD;
                s2_addr     <= s_imc_32.WR_ADDR;
            end
            3'b100:begin
                get_addr_2  <= s_imc_42.WR_VLD;
                s2_addr     <= s_imc_42.WR_ADDR;
            end
            3'b101:begin
                get_addr_2  <= s_imc_52.WR_VLD;
                s2_addr     <= s_imc_52.WR_ADDR;
            end
            3'b110:begin
                get_addr_2  <= s_imc_62.WR_VLD;
                s2_addr     <= s_imc_62.WR_ADDR;
            end
            3'b111:begin
                get_addr_2  <= s_imc_72.WR_VLD;
                s2_addr     <= s_imc_72.WR_ADDR;
            end
        endcase
    end
    else begin
        get_addr_2  <=   '0;
        if(sram_cache_c_2==IDLE)begin
            s2_addr    <=   '0;
        end
        else
            s2_addr    <=   s2_addr;
    end
end 
always_ff @(posedge CLK or negedge RST_N) begin
    if(!RST_N)begin
        get_addr_3 <= '0;
        s3_addr   <= '0;
    end
    else if(sram_cache_c_3==GET_ADDR)begin
        case(s3_pri)
            3'b000:begin
                get_addr_3  <= s_imc_03.WR_VLD;
                s3_addr     <= s_imc_03.WR_ADDR;
            end
            3'b001:begin
                get_addr_3  <= s_imc_13.WR_VLD;
                s3_addr     <= s_imc_13.WR_ADDR;
            end
            3'b010:begin
                get_addr_3  <= s_imc_23.WR_VLD;
                s3_addr     <= s_imc_23.WR_ADDR;
            end
            3'b011:begin
                get_addr_3  <= s_imc_33.WR_VLD;
                s3_addr     <= s_imc_33.WR_ADDR;
            end
            3'b100:begin
                get_addr_3  <= s_imc_43.WR_VLD;
                s3_addr     <= s_imc_43.WR_ADDR;
            end
            3'b101:begin
                get_addr_3  <= s_imc_53.WR_VLD;
                s3_addr     <= s_imc_53.WR_ADDR;
            end
            3'b110:begin
                get_addr_3  <= s_imc_63.WR_VLD;
                s3_addr     <= s_imc_63.WR_ADDR;
            end
            3'b111:begin
                get_addr_3  <= s_imc_73.WR_VLD;
                s3_addr     <= s_imc_73.WR_ADDR;
            end
        endcase
    end
    else begin
        get_addr_3  <=   '0;
        if(sram_cache_c_3==IDLE)begin
            s3_addr    <=   '0;
        end
        else
            s3_addr    <=   s3_addr;
    end
end 
//------------------------------------------------------------------------------------------//
//------------------------------------------------------------------------------------------//
//tran addr to cac fifo_ctrl wr_addr_gen
//-------tran addr to cac
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_00.WR_DATA_VLD    <= '0;
        s_imc_00.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_0==TRAN_ADDR && fix_pri==3'b000 && !s_imc_00.WR_DATA_VLD)begin
        s_imc_00.WR_DATA_VLD    <= 1'b1;
        s_imc_00.WR_DATA_VALUE  <= {{2'b00},fix_addr,fix_size};    
    end
    else 
        s_imc_00.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_10.WR_DATA_VLD    <= '0;
        s_imc_10.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_0==TRAN_ADDR && fix_pri==3'b001&& !s_imc_10.WR_DATA_VLD)begin
        s_imc_10.WR_DATA_VLD    <= 1'b1;
        s_imc_10.WR_DATA_VALUE  <= {{2'b00},fix_addr,fix_size};    
    end
    else 
        s_imc_10.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_20.WR_DATA_VLD    <= '0;
        s_imc_20.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_0==TRAN_ADDR && fix_pri==3'b010&& !s_imc_20.WR_DATA_VLD)begin
        s_imc_20.WR_DATA_VLD    <= 1'b1;
        s_imc_20.WR_DATA_VALUE  <= {{2'b00},fix_addr,fix_size};    
    end
    else 
        s_imc_20.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_30.WR_DATA_VLD    <= '0;
        s_imc_30.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_0==TRAN_ADDR && fix_pri==3'b011&& !s_imc_30.WR_DATA_VLD)begin
        s_imc_30.WR_DATA_VLD    <= 1'b1;
        s_imc_30.WR_DATA_VALUE  <= {{2'b00},fix_addr,fix_size};    
    end
    else 
        s_imc_30.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_40.WR_DATA_VLD    <= '0;
        s_imc_40.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_0==TRAN_ADDR && fix_pri==3'b100&& !s_imc_40.WR_DATA_VLD)begin
        s_imc_40.WR_DATA_VLD    <= 1'b1;
        s_imc_40.WR_DATA_VALUE  <= {{2'b00},fix_addr,fix_size};    
    end
    else 
        s_imc_40.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_50.WR_DATA_VLD    <= '0;
        s_imc_50.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_0==TRAN_ADDR && fix_pri==3'b101&& !s_imc_50.WR_DATA_VLD)begin
        s_imc_50.WR_DATA_VLD    <= 1'b1;
        s_imc_50.WR_DATA_VALUE  <= {{2'b00},fix_addr,fix_size};    
    end
    else 
        s_imc_50.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_60.WR_DATA_VLD    <= '0;
        s_imc_60.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_0==TRAN_ADDR && fix_pri==3'b110&& !s_imc_60.WR_DATA_VLD)begin
        s_imc_60.WR_DATA_VLD    <= 1'b1;
        s_imc_60.WR_DATA_VALUE  <= {{2'b00},fix_addr,fix_size};    
    end
    else 
        s_imc_60.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_70.WR_DATA_VLD    <= '0;
        s_imc_70.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_0==TRAN_ADDR && fix_pri==3'b111&& !s_imc_70.WR_DATA_VLD)begin
        s_imc_70.WR_DATA_VLD    <= 1'b1;
        s_imc_70.WR_DATA_VALUE  <= {{2'b00},fix_addr,fix_size};    
    end
    else 
        s_imc_70.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_01.WR_DATA_VLD    <= '0;
        s_imc_01.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_1==TRAN_ADDR && s1_pri==3'b000&& !s_imc_01.WR_DATA_VLD)begin
        s_imc_01.WR_DATA_VLD    <= 1'b1;
        s_imc_01.WR_DATA_VALUE  <= {{2'b00},s1_addr,s1_size};    
    end
    else 
        s_imc_01.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_11.WR_DATA_VLD    <= '0;
        s_imc_11.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_1==TRAN_ADDR && s1_pri==3'b001&& !s_imc_11.WR_DATA_VLD)begin
        s_imc_11.WR_DATA_VLD    <= 1'b1;
        s_imc_11.WR_DATA_VALUE  <= {{2'b00},s1_addr,s1_size};    
    end
    else 
        s_imc_11.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_21.WR_DATA_VLD    <= '0;
        s_imc_21.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_1==TRAN_ADDR && s1_pri==3'b010&& !s_imc_21.WR_DATA_VLD)begin
        s_imc_21.WR_DATA_VLD    <= 1'b1;
        s_imc_21.WR_DATA_VALUE  <= {{2'b00},s1_addr,s1_size};    
    end
    else 
        s_imc_21.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_31.WR_DATA_VLD    <= '0;
        s_imc_31.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_1==TRAN_ADDR && s1_pri==3'b011&& !s_imc_31.WR_DATA_VLD)begin
        s_imc_31.WR_DATA_VLD    <= 1'b1;
        s_imc_31.WR_DATA_VALUE  <= {{2'b00},s1_addr,s1_size};    
    end
    else 
        s_imc_31.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_41.WR_DATA_VLD    <= '0;
        s_imc_41.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_1==TRAN_ADDR && s1_pri==3'b100&& !s_imc_41.WR_DATA_VLD)begin
        s_imc_41.WR_DATA_VLD    <= 1'b1;
        s_imc_41.WR_DATA_VALUE  <= {{2'b00},s1_addr,s1_size};    
    end
    else 
        s_imc_41.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_51.WR_DATA_VLD    <= '0;
        s_imc_51.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_1==TRAN_ADDR && s1_pri==3'b101&& !s_imc_51.WR_DATA_VLD)begin
        s_imc_51.WR_DATA_VLD    <= 1'b1;
        s_imc_51.WR_DATA_VALUE  <= {{2'b00},s1_addr,s1_size};    
    end
    else        
        s_imc_51.WR_DATA_VLD    <= '0;
end
 
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_61.WR_DATA_VLD    <= '0;
        s_imc_61.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_1==TRAN_ADDR && s1_pri==3'b110&& !s_imc_61.WR_DATA_VLD)begin
        s_imc_61.WR_DATA_VLD    <= 1'b1;
        s_imc_61.WR_DATA_VALUE  <= {{2'b00},s1_addr,s1_size};    
    end
    else 
        s_imc_61.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_71.WR_DATA_VLD    <= '0;
        s_imc_71.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_1==TRAN_ADDR && s1_pri==3'b111&& !s_imc_71.WR_DATA_VLD)begin
        s_imc_71.WR_DATA_VLD    <= 1'b1;
        s_imc_71.WR_DATA_VALUE  <= {{2'b00},s1_addr,s1_size};    
    end
    else 
        s_imc_71.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_02.WR_DATA_VLD    <= '0;
        s_imc_02.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_2==TRAN_ADDR && s2_pri==3'b000&& !s_imc_02.WR_DATA_VLD)begin
        s_imc_02.WR_DATA_VLD    <= 1'b1;
        s_imc_02.WR_DATA_VALUE  <= {{2'b00},s2_addr,s2_size};    
    end
    else 
        s_imc_02.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_12.WR_DATA_VLD    <= '0;
        s_imc_12.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_2==TRAN_ADDR && s2_pri==3'b001&& !s_imc_12.WR_DATA_VLD)begin
        s_imc_12.WR_DATA_VLD    <= 1'b1;
        s_imc_12.WR_DATA_VALUE  <= {{2'b00},s2_addr,s2_size};    
    end
    else 
        s_imc_12.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_22.WR_DATA_VLD    <= '0;
        s_imc_22.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_2==TRAN_ADDR && s2_pri==3'b010&& !s_imc_22.WR_DATA_VLD)begin
        s_imc_22.WR_DATA_VLD    <= 1'b1;
        s_imc_22.WR_DATA_VALUE  <= {{2'b00},s2_addr,s2_size};    
    end
    else 
        s_imc_22.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_32.WR_DATA_VLD    <= '0;
        s_imc_32.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_2==TRAN_ADDR && s2_pri==3'b011&& !s_imc_32.WR_DATA_VLD)begin
        s_imc_32.WR_DATA_VLD    <= 1'b1;
        s_imc_32.WR_DATA_VALUE  <= {{2'b00},s2_addr,s2_size};    
    end
    else 
        s_imc_32.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_42.WR_DATA_VLD    <= '0;
        s_imc_42.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_2==TRAN_ADDR && s2_pri==3'b100&& !s_imc_42.WR_DATA_VLD)begin
        s_imc_42.WR_DATA_VLD    <= 1'b1;
        s_imc_42.WR_DATA_VALUE  <= {{2'b00},s2_addr,s2_size};    
    end
    else 
        s_imc_42.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_52.WR_DATA_VLD    <= '0;
        s_imc_52.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_2==TRAN_ADDR && s2_pri==3'b101&& !s_imc_52.WR_DATA_VLD)begin
        s_imc_52.WR_DATA_VLD    <= 1'b1;
        s_imc_52.WR_DATA_VALUE  <= {{2'b00},s2_addr,s2_size};    
    end
    else
        s_imc_52.WR_DATA_VLD    <= '0;
end

always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_62.WR_DATA_VLD    <= '0;
        s_imc_62.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_2==TRAN_ADDR && s2_pri==3'b110&& !s_imc_62.WR_DATA_VLD)begin
        s_imc_62.WR_DATA_VLD    <= 1'b1;
        s_imc_62.WR_DATA_VALUE  <= {{2'b00},s2_addr,s2_size};    
    end
    else 
        s_imc_62.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_72.WR_DATA_VLD    <= '0;
        s_imc_72.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_2==TRAN_ADDR && s2_pri==3'b111&& !s_imc_72.WR_DATA_VLD)begin
        s_imc_72.WR_DATA_VLD    <= 1'b1;
        s_imc_72.WR_DATA_VALUE  <= {{2'b00},s2_addr,s2_size};    
    end
    else 
        s_imc_72.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_03.WR_DATA_VLD    <= '0;
        s_imc_03.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_3==TRAN_ADDR && s3_pri==3'b000&& !s_imc_03.WR_DATA_VLD)begin
        s_imc_03.WR_DATA_VLD    <= 1'b1;
        s_imc_03.WR_DATA_VALUE  <= {{2'b00},s3_addr,s3_size};    
    end
    else 
        s_imc_03.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_13.WR_DATA_VLD    <= '0;
        s_imc_13.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_3==TRAN_ADDR && s3_pri==3'b001&& !s_imc_13.WR_DATA_VLD)begin
        s_imc_13.WR_DATA_VLD    <= 1'b1;
        s_imc_13.WR_DATA_VALUE  <= {{2'b00},s3_addr,s3_size};    
    end
    else 
        s_imc_13.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_23.WR_DATA_VLD    <= '0;
        s_imc_23.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_3==TRAN_ADDR && s3_pri==3'b010&& !s_imc_23.WR_DATA_VLD)begin
        s_imc_23.WR_DATA_VLD    <= 1'b1;
        s_imc_23.WR_DATA_VALUE  <= {{2'b00},s3_addr,s3_size};    
    end
    else 
        s_imc_23.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_33.WR_DATA_VLD    <= '0;
        s_imc_33.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_3==TRAN_ADDR && s3_pri==3'b011&& !s_imc_33.WR_DATA_VLD)begin
        s_imc_33.WR_DATA_VLD    <= 1'b1;
        s_imc_33.WR_DATA_VALUE  <= {{2'b00},s3_addr,s3_size};    
    end
    else 
        s_imc_33.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_43.WR_DATA_VLD    <= '0;
        s_imc_43.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_3==TRAN_ADDR && s3_pri==3'b100&& !s_imc_43.WR_DATA_VLD)begin
        s_imc_43.WR_DATA_VLD    <= 1'b1;
        s_imc_43.WR_DATA_VALUE  <= {{2'b00},s3_addr,s3_size};    
    end
    else 
        s_imc_43.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_53.WR_DATA_VLD    <= '0;
        s_imc_53.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_3==TRAN_ADDR && s3_pri==3'b101&& !s_imc_53.WR_DATA_VLD)begin
        s_imc_53.WR_DATA_VLD    <= 1'b1;
        s_imc_53.WR_DATA_VALUE  <= {{2'b00},s3_addr,s3_size};    
    end
    else
        s_imc_53.WR_DATA_VLD    <= '0;
end

always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_63.WR_DATA_VLD    <= '0;
        s_imc_63.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_3==TRAN_ADDR && s3_pri==3'b110&& !s_imc_63.WR_DATA_VLD)begin
        s_imc_63.WR_DATA_VLD    <= 1'b1;
        s_imc_63.WR_DATA_VALUE  <= {{2'b00},s3_addr,s3_size};    
    end
    else 
        s_imc_63.WR_DATA_VLD    <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_imc_73.WR_DATA_VLD    <= '0;
        s_imc_73.WR_DATA_VALUE  <= '0;
    end
    else if(sram_cache_c_3==TRAN_ADDR && s3_pri==3'b111&& !s_imc_73.WR_DATA_VLD)begin
        s_imc_73.WR_DATA_VLD    <= 1'b1;
        s_imc_73.WR_DATA_VALUE  <= {{2'b00},s3_addr,s3_size};    
    end
    else 
        s_imc_73.WR_DATA_VLD    <= '0;
end
//-------tran addr to cac-------------------



//-------tran addr to wr_addr_gen----------
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        wa_s_0.SOP  <= '0;
        wa_s_0.ADDR <= '0;
    end
    else if(wa_s_0.SOP)begin
        wa_s_0.SOP  <= '0;
        wa_s_0.ADDR <= '0;
    end
    else if(sram_cache_c_0==TRAN_ADDR)begin
        wa_s_0.SOP  <= 1'b1;
        wa_s_0.ADDR <= fix_addr;
    end
    else
        wa_s_0.SOP  <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        wa_s_1.SOP  <= '0;
        wa_s_1.ADDR <= '0;
    end
    else if(wa_s_1.SOP)begin
        wa_s_1.SOP  <= '0;
        wa_s_1.ADDR <= '0;
    end
    else if(sram_cache_c_1==TRAN_ADDR)begin
        wa_s_1.SOP  <= 1'b1;
        wa_s_1.ADDR <= s1_addr;
    end
    else
        wa_s_1.SOP  <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        wa_s_2.SOP  <= '0;
        wa_s_2.ADDR <= '0;
    end
    else if(wa_s_2.SOP)begin
        wa_s_2.SOP  <= '0;
        wa_s_2.ADDR <= '0;
    end
    else if(sram_cache_c_2==TRAN_ADDR)begin
        wa_s_2.SOP  <= 1'b1;
        wa_s_2.ADDR <= s2_addr;
    end
    else
        wa_s_2.SOP  <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        wa_s_3.SOP  <= '0;
        wa_s_3.ADDR <= '0;
    end
    else if(wa_s_3.SOP)begin
        wa_s_3.SOP  <= '0;
        wa_s_3.ADDR <= '0;
    end
    else if(sram_cache_c_3==TRAN_ADDR)begin
        wa_s_3.SOP  <= 1'b1;
        wa_s_3.ADDR <= s3_addr;
    end
    else
        wa_s_3.SOP  <= '0;
end
//-------tran addr to wr_addr_gen----------


//-------tran addr to fifo ctrl -----------
logic   [0:0]   push_done_00;
logic   [0:0]   push_done_01;
logic   [0:0]   push_done_02;
logic   [0:0]   push_done_03;
logic   [0:0]   push_done_10;
logic   [0:0]   push_done_11;
logic   [0:0]   push_done_12;
logic   [0:0]   push_done_13;
logic   [0:0]   push_done_20;
logic   [0:0]   push_done_21;
logic   [0:0]   push_done_22;
logic   [0:0]   push_done_23;
logic   [0:0]   push_done_30;
logic   [0:0]   push_done_31;
logic   [0:0]   push_done_32;
logic   [0:0]   push_done_33;
logic   [0:0]   push_done_40;
logic   [0:0]   push_done_41;
logic   [0:0]   push_done_42;
logic   [0:0]   push_done_43;
logic   [0:0]   push_done_50;
logic   [0:0]   push_done_51;
logic   [0:0]   push_done_52;
logic   [0:0]   push_done_53;
logic   [0:0]   push_done_60;
logic   [0:0]   push_done_61;
logic   [0:0]   push_done_62;
logic   [0:0]   push_done_63;
logic   [0:0]   push_done_70;
logic   [0:0]   push_done_71;
logic   [0:0]   push_done_72;
logic   [0:0]   push_done_73;
st_fifo_bus#(.FIFO_WIDTH(28))   st_fifo_0(.CLK(CLK),
                                          .RST_N(RST_N)
                                         );
st_fifo_bus#(.FIFO_WIDTH(28))   st_fifo_1(.CLK(CLK),
                                          .RST_N(RST_N)
                                         );
st_fifo_bus#(.FIFO_WIDTH(28))   st_fifo_2(.CLK(CLK),
                                          .RST_N(RST_N)
                                         );
st_fifo_bus#(.FIFO_WIDTH(28))   st_fifo_3(.CLK(CLK),
                                          .RST_N(RST_N)
                                         );
st_fifo_bus#(.FIFO_WIDTH(28))   st_fifo_4(.CLK(CLK),
                                          .RST_N(RST_N)
                                         );
st_fifo_bus#(.FIFO_WIDTH(28))   st_fifo_5(.CLK(CLK),
                                          .RST_N(RST_N)
                                         );
st_fifo_bus#(.FIFO_WIDTH(28))   st_fifo_6(.CLK(CLK),
                                          .RST_N(RST_N)
                                         );
st_fifo_bus#(.FIFO_WIDTH(28))   st_fifo_7(.CLK(CLK),
                                          .RST_N(RST_N)
                                         );
fifo_ctrl#(.FIFO_WIDTH(28),
           .FIFO_DEPTH(256))    fc_0(.bus(st_fifo_0.fifo));
fifo_ctrl#(.FIFO_WIDTH(28),
           .FIFO_DEPTH(256))    fc_1(.bus(st_fifo_1.fifo));
fifo_ctrl#(.FIFO_WIDTH(28),
           .FIFO_DEPTH(256))    fc_2(.bus(st_fifo_2.fifo));
fifo_ctrl#(.FIFO_WIDTH(28),
           .FIFO_DEPTH(256))    fc_3(.bus(st_fifo_3.fifo));
fifo_ctrl#(.FIFO_WIDTH(28),
           .FIFO_DEPTH(256))    fc_4(.bus(st_fifo_4.fifo));
fifo_ctrl#(.FIFO_WIDTH(28),
           .FIFO_DEPTH(256))    fc_5(.bus(st_fifo_5.fifo));
fifo_ctrl#(.FIFO_WIDTH(28),
           .FIFO_DEPTH(256))    fc_6(.bus(st_fifo_6.fifo));
fifo_ctrl#(.FIFO_WIDTH(28),
           .FIFO_DEPTH(256))    fc_7(.bus(st_fifo_7.fifo));
//push addr and data_size to fifo_ctrl
assign st_fifo_0.CLEAR = 0;
assign st_fifo_1.CLEAR = 0;
assign st_fifo_2.CLEAR = 0;
assign st_fifo_3.CLEAR = 0;
assign st_fifo_4.CLEAR = 0;
assign st_fifo_5.CLEAR = 0;
assign st_fifo_6.CLEAR = 0;
assign st_fifo_7.CLEAR = 0;
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        st_fifo_0.WR_EN <= '0;
        push_done_00    <= '0;
        push_done_01    <= '0;
        push_done_02    <= '0;
        push_done_03    <= '0;
    end
    else if(sram_cache_c_0==TRAN_ADDR&&fix_pri==3'b000&&!push_done_00)begin
        st_fifo_0.WR_EN<=  1'b1;
        st_fifo_0.WR_DATA<= {fix_addr,fix_size};
        push_done_00   <=  1'b1;
    end
    else if(sram_cache_c_1==TRAN_ADDR&&s1_pri==3'b000&&!push_done_01)begin
        st_fifo_0.WR_EN<=  1'b1;
        push_done_01   <=  1'b1;
        st_fifo_0.WR_DATA<= {s1_addr,s1_size};
    end
    else if(sram_cache_c_2==TRAN_ADDR&&s2_pri==3'b000&&!push_done_02)begin
        st_fifo_0.WR_EN<=  1'b1;
        push_done_02   <=  1'b1;
        st_fifo_0.WR_DATA<= {s2_addr,s2_size};
    end
    else if(sram_cache_c_3==TRAN_ADDR&&s2_pri==3'b000&&!push_done_03)begin
        st_fifo_0.WR_EN<=  1'b1;
        push_done_03   <=  1'b1;
        st_fifo_0.WR_DATA<= {s3_addr,s3_size};
    end
    else if(st_fifo_0.WR_EN)
        st_fifo_0.WR_EN<= '0;
    else if(sram_cache_c_0==TRAN_DATA)
        push_done_00   <=  '0;
    else if(sram_cache_c_1==TRAN_DATA)
        push_done_01   <=  '0;
    else if(sram_cache_c_2==TRAN_DATA)
        push_done_02   <=  '0;
    else if(sram_cache_c_3==TRAN_DATA)
        push_done_03   <=  '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        st_fifo_1.WR_EN <= '0;
        push_done_10    <= '0;
        push_done_11    <= '0;
        push_done_12    <= '0;
        push_done_13    <= '0;
    end
    else if(sram_cache_c_0==TRAN_ADDR&&fix_pri==3'b001&&!push_done_10)begin
        st_fifo_1.WR_EN<=  1'b1;
        st_fifo_1.WR_DATA<= {fix_addr,fix_size};
        push_done_10   <=  1'b1;
    end
    else if(sram_cache_c_1==TRAN_ADDR&&s1_pri==3'b001&&!push_done_11)begin
        st_fifo_1.WR_EN<=  1'b1;
        push_done_11   <=  1'b1;
        st_fifo_1.WR_DATA<= {s1_addr,s1_size};
    end
    else if(sram_cache_c_2==TRAN_ADDR&&s2_pri==3'b001&&!push_done_12)begin
        st_fifo_1.WR_EN<=  1'b1;
        push_done_12   <=  1'b1;
        st_fifo_1.WR_DATA<= {s2_addr,s2_size};
    end
    else if(sram_cache_c_3==TRAN_ADDR&&s2_pri==3'b001&&!push_done_13)begin
        st_fifo_1.WR_EN<=  1'b1;
        push_done_13   <=  1'b1;
        st_fifo_1.WR_DATA<= {s3_addr,s3_size};
    end
    else if(st_fifo_1.WR_EN)
        st_fifo_1.WR_EN<= '0;
    else if(sram_cache_c_0==TRAN_DATA)
        push_done_10   <=  '0;
    else if(sram_cache_c_1==TRAN_DATA)
        push_done_11   <=  '0;
    else if(sram_cache_c_2==TRAN_DATA)
        push_done_12   <=  '0;
    else if(sram_cache_c_3==TRAN_DATA)
        push_done_13   <=  '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        st_fifo_2.WR_EN <= '0;
        push_done_20    <= '0;
        push_done_21    <= '0;
        push_done_22    <= '0;
        push_done_23    <= '0;
    end
    else if(sram_cache_c_0==TRAN_ADDR&&fix_pri==3'b010&&!push_done_20)begin
        st_fifo_2.WR_EN<=  1'b1;
        st_fifo_2.WR_DATA<= {fix_addr,fix_size};
        push_done_20   <=  1'b1;
    end
    else if(sram_cache_c_1==TRAN_ADDR&&s1_pri==3'b010&&!push_done_21)begin
        st_fifo_2.WR_EN<=  1'b1;
        push_done_21   <=  1'b1;
        st_fifo_2.WR_DATA<= {s1_addr,s1_size};
    end
    else if(sram_cache_c_2==TRAN_ADDR&&s2_pri==3'b010&&!push_done_22)begin
        st_fifo_2.WR_EN<=  1'b1;
        push_done_22   <=  1'b1;
        st_fifo_2.WR_DATA<= {s2_addr,s2_size};
    end
    else if(sram_cache_c_3==TRAN_ADDR&&s2_pri==3'b010&&!push_done_23)begin
        st_fifo_2.WR_EN<=  1'b1;
        push_done_23   <=  1'b1;
        st_fifo_2.WR_DATA<= {s3_addr,s3_size};
    end
    else if(st_fifo_2.WR_EN)
        st_fifo_2.WR_EN<= '0;
    else if(sram_cache_c_0==TRAN_DATA)
        push_done_20   <=  '0;
    else if(sram_cache_c_1==TRAN_DATA)
        push_done_21   <=  '0;
    else if(sram_cache_c_2==TRAN_DATA)
        push_done_22   <=  '0;
    else if(sram_cache_c_3==TRAN_DATA)
        push_done_23   <=  '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        st_fifo_3.WR_EN <= '0;
        push_done_30    <= '0;
        push_done_31    <= '0;
        push_done_32    <= '0;
        push_done_33    <= '0;
    end
    else if(sram_cache_c_0==TRAN_ADDR&&fix_pri==3'b011&&!push_done_30)begin
        st_fifo_3.WR_EN<=  1'b1;
        st_fifo_3.WR_DATA<= {fix_addr,fix_size};
        push_done_30   <=  1'b1;
    end
    else if(sram_cache_c_1==TRAN_ADDR&&s1_pri==3'b011&&!push_done_31)begin
        st_fifo_3.WR_EN<=  1'b1;
        push_done_31   <=  1'b1;
        st_fifo_3.WR_DATA<= {s1_addr,s1_size};
    end
    else if(sram_cache_c_2==TRAN_ADDR&&s2_pri==3'b011&&!push_done_32)begin
        st_fifo_3.WR_EN<=  1'b1;
        push_done_32   <=  1'b1;
        st_fifo_3.WR_DATA<= {s2_addr,s2_size};
    end
    else if(sram_cache_c_3==TRAN_ADDR&&s2_pri==3'b011&&!push_done_33)begin
        st_fifo_3.WR_EN<=  1'b1;
        push_done_33   <=  1'b1;
        st_fifo_3.WR_DATA<= {s3_addr,s3_size};
    end
    else if(st_fifo_3.WR_EN)
        st_fifo_3.WR_EN<= '0;
    else if(sram_cache_c_0==TRAN_DATA)
        push_done_30   <=  '0;
    else if(sram_cache_c_1==TRAN_DATA)
        push_done_31   <=  '0;
    else if(sram_cache_c_2==TRAN_DATA)
        push_done_32   <=  '0;
    else if(sram_cache_c_3==TRAN_DATA)
        push_done_33   <=  '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        st_fifo_4.WR_EN <= '0;
        push_done_40    <= '0;
        push_done_41    <= '0;
        push_done_42    <= '0;
        push_done_43    <= '0;
    end
    else if(sram_cache_c_0==TRAN_ADDR&&fix_pri==3'b100&&!push_done_40)begin
        st_fifo_4.WR_EN<=  1'b1;
        st_fifo_4.WR_DATA<= {fix_addr,fix_size};
        push_done_40   <=  1'b1;
    end
    else if(sram_cache_c_1==TRAN_ADDR&&s1_pri==3'b100&&!push_done_41)begin
        st_fifo_4.WR_EN<=  1'b1;
        push_done_41   <=  1'b1;
        st_fifo_4.WR_DATA<= {s1_addr,s1_size};
    end
    else if(sram_cache_c_2==TRAN_ADDR&&s2_pri==3'b100&&!push_done_42)begin
        st_fifo_4.WR_EN<=  1'b1;
        push_done_42   <=  1'b1;
        st_fifo_4.WR_DATA<= {s2_addr,s2_size};
    end
    else if(sram_cache_c_3==TRAN_ADDR&&s2_pri==3'b100&&!push_done_43)begin
        st_fifo_4.WR_EN<=  1'b1;
        push_done_43   <=  1'b1;
        st_fifo_4.WR_DATA<= {s3_addr,s3_size};
    end
    else if(st_fifo_4.WR_EN)
        st_fifo_4.WR_EN<= '0;
    else if(sram_cache_c_0==TRAN_DATA)
        push_done_40   <=  '0;
    else if(sram_cache_c_1==TRAN_DATA)
        push_done_41   <=  '0;
    else if(sram_cache_c_2==TRAN_DATA)
        push_done_42   <=  '0;
    else if(sram_cache_c_3==TRAN_DATA)
        push_done_43   <=  '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        st_fifo_5.WR_EN <= '0;
        push_done_50    <= '0;
        push_done_51    <= '0;
        push_done_52    <= '0;
        push_done_53    <= '0;
    end
    else if(sram_cache_c_0==TRAN_ADDR&&fix_pri==3'b101&&!push_done_50)begin
        st_fifo_5.WR_EN<=  1'b1;
        st_fifo_5.WR_DATA<= {fix_addr,fix_size};
        push_done_50   <=  1'b1;
    end
    else if(sram_cache_c_1==TRAN_ADDR&&s1_pri==3'b101&&!push_done_51)begin
        st_fifo_5.WR_EN<=  1'b1;
        push_done_51   <=  1'b1;
        st_fifo_5.WR_DATA<= {s1_addr,s1_size};
    end
    else if(sram_cache_c_2==TRAN_ADDR&&s2_pri==3'b101&&!push_done_52)begin
        st_fifo_5.WR_EN<=  1'b1;
        push_done_52   <=  1'b1;
        st_fifo_5.WR_DATA<= {s2_addr,s2_size};
    end
    else if(sram_cache_c_3==TRAN_ADDR&&s2_pri==3'b101&&!push_done_53)begin
        st_fifo_5.WR_EN<=  1'b1;
        push_done_53   <=  1'b1;
        st_fifo_5.WR_DATA<= {s3_addr,s3_size};
    end
    else if(st_fifo_5.WR_EN)
        st_fifo_5.WR_EN<= '0;
    else if(sram_cache_c_0==TRAN_DATA)
        push_done_50   <=  '0;
    else if(sram_cache_c_1==TRAN_DATA)
        push_done_51   <=  '0;
    else if(sram_cache_c_2==TRAN_DATA)
        push_done_52   <=  '0;
    else if(sram_cache_c_3==TRAN_DATA)
        push_done_53   <=  '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        st_fifo_6.WR_EN <= '0;
        push_done_60    <= '0;
        push_done_61    <= '0;
        push_done_62    <= '0;
        push_done_63    <= '0;
    end
    else if(sram_cache_c_0==TRAN_ADDR&&fix_pri==3'b110&&!push_done_60)begin
        st_fifo_6.WR_EN<=  1'b1;
        st_fifo_6.WR_DATA<= {fix_addr,fix_size};
        push_done_60   <=  1'b1;
    end
    else if(sram_cache_c_1==TRAN_ADDR&&s1_pri==3'b110&&!push_done_61)begin
        st_fifo_6.WR_EN<=  1'b1;
        push_done_61   <=  1'b1;
        st_fifo_6.WR_DATA<= {s1_addr,s1_size};
    end
    else if(sram_cache_c_2==TRAN_ADDR&&s2_pri==3'b110&&!push_done_62)begin
        st_fifo_6.WR_EN<=  1'b1;
        push_done_62   <=  1'b1;
        st_fifo_6.WR_DATA<= {s2_addr,s2_size};
    end
    else if(sram_cache_c_3==TRAN_ADDR&&s2_pri==3'b110&&!push_done_63)begin
        st_fifo_6.WR_EN<=  1'b1;
        push_done_63   <=  1'b1;
        st_fifo_6.WR_DATA<= {s3_addr,s3_size};
    end
    else if(st_fifo_6.WR_EN)
        st_fifo_6.WR_EN<= '0;
    else if(sram_cache_c_0==TRAN_DATA)
        push_done_60   <=  '0;
    else if(sram_cache_c_1==TRAN_DATA)
        push_done_61   <=  '0;
    else if(sram_cache_c_2==TRAN_DATA)
        push_done_62   <=  '0;
    else if(sram_cache_c_3==TRAN_DATA)
        push_done_63   <=  '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        st_fifo_7.WR_EN <= '0;
        push_done_70    <= '0;
        push_done_71    <= '0;
        push_done_72    <= '0;
        push_done_73    <= '0;
    end
    else if(sram_cache_c_0==TRAN_ADDR&&fix_pri==3'b111&&!push_done_70)begin
        st_fifo_7.WR_EN<=  1'b1;
        st_fifo_7.WR_DATA<= {fix_addr,fix_size};
        push_done_70   <=  1'b1;
    end
    else if(sram_cache_c_1==TRAN_ADDR&&s1_pri==3'b111&&!push_done_71)begin
        st_fifo_7.WR_EN<=  1'b1;
        push_done_71   <=  1'b1;
        st_fifo_7.WR_DATA<= {s1_addr,s1_size};
    end
    else if(sram_cache_c_2==TRAN_ADDR&&s2_pri==3'b111&&!push_done_72)begin
        st_fifo_7.WR_EN<=  1'b1;
        push_done_72   <=  1'b1;
        st_fifo_7.WR_DATA<= {s2_addr,s2_size};
    end
    else if(sram_cache_c_3==TRAN_ADDR&&s2_pri==3'b111&&!push_done_73)begin
        st_fifo_7.WR_EN<=  1'b1;
        push_done_73   <=  1'b1;
        st_fifo_7.WR_DATA<= {s3_addr,s3_size};
    end
    else if(st_fifo_7.WR_EN)
        st_fifo_7.WR_EN<= '0;
    else if(sram_cache_c_0==TRAN_DATA)
        push_done_70   <=  '0;
    else if(sram_cache_c_1==TRAN_DATA)
        push_done_71   <=  '0;
    else if(sram_cache_c_2==TRAN_DATA)
        push_done_72   <=  '0;
    else if(sram_cache_c_3==TRAN_DATA)
        push_done_73   <=  '0;
end
//-------tran addr to fifo ctrl -----------
//-------tran addr done (tran_addr only takes one cycle)---
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        tran_addr_done_0    <='0;   
    end
    else if(sram_cache_c_0==TRAN_ADDR)
        tran_addr_done_0    <= 1'b1;
    else
        tran_addr_done_0    <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        tran_addr_done_1    <='0;   
    end
    else if(sram_cache_c_1==TRAN_ADDR)
        tran_addr_done_1    <= 1'b1;
    else
        tran_addr_done_1    <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        tran_addr_done_2    <='0;   
    end
    else if(sram_cache_c_2==TRAN_ADDR)
        tran_addr_done_2    <= 1'b1;
    else
        tran_addr_done_2    <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        tran_addr_done_3    <='0;   
    end
    else if(sram_cache_c_3==TRAN_ADDR)
        tran_addr_done_3    <= 1'b1;
    else
        tran_addr_done_3    <= 1'b0;
end

//-------tran addr done (tran_addr only takes one cycle)---
//tran addr to cac fifo_ctrl wr_addr_gen
//------------------------------------------------------------------------------------------//
//tran data to wr_addr_gen
logic   [0:0]   rec_eop_0;
logic   [0:0]   rec_eop_1;
logic   [0:0]   rec_eop_2;
logic   [0:0]   rec_eop_3;
assign  wa_s_0.DATA =   tran_data_0;
assign  wa_s_1.DATA =   tran_data_1;
assign  wa_s_2.DATA =   tran_data_2;
assign  wa_s_3.DATA =   tran_data_3;
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        wa_s_0.VLD    <='0;
    end
    else begin
        wa_s_0.VLD    <= fifo_pop_0;
    end
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        wa_s_1.VLD    <='0;
    end
    else begin
        wa_s_1.VLD    <= fifo_pop_1;
    end
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        wa_s_2.VLD    <='0;
    end
    else begin
        wa_s_2.VLD    <= fifo_pop_2;
    end
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        wa_s_3.VLD    <='0;
    end
    else begin
        wa_s_3.VLD    <= fifo_pop_3;
    end
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        rec_eop_0   <= '0;
    end
    else if(cc_s.WR_EOP0)begin
        rec_eop_0   <= 1'b1;
    end
    else if(wa_s_0.EOP)
        rec_eop_0   <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        wa_s_0.EOP  <= '0;
    end
    else if(rec_eop_0 && fifo_empty_0 && !wa_s_0.EOP)
        wa_s_0.EOP  <= 1'b1;
    else
        wa_s_0.EOP  <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        rec_eop_1   <= '0;
    end
    else if(cc_s.WR_EOP1)begin
        rec_eop_1   <= 1'b1;
    end
    else if(wa_s_1.EOP)
        rec_eop_1   <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        wa_s_1.EOP  <= '0;
    end
    else if(rec_eop_1 && fifo_empty_1 && !wa_s_1.EOP)
        wa_s_1.EOP  <= 1'b1;
    else
        wa_s_1.EOP  <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        rec_eop_2   <= '0;
    end
    else if(cc_s.WR_EOP2)begin
        rec_eop_2   <= 1'b1;
    end
    else if(wa_s_2.EOP)
        rec_eop_2   <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        wa_s_2.EOP  <= '0;
    end
    else if(rec_eop_2 && fifo_empty_2 && !wa_s_2.EOP)
        wa_s_2.EOP  <= 1'b1;
    else
        wa_s_2.EOP  <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        rec_eop_3   <= '0;
    end
    else if(cc_s.WR_EOP3)begin
        rec_eop_3   <= 1'b1;
    end
    else if(wa_s_3.EOP)
        rec_eop_3   <= '0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        wa_s_3.EOP  <= '0;
    end
    else if(rec_eop_3 && fifo_empty_3 && !wa_s_3.EOP)
        wa_s_3.EOP  <= 1'b1;
    else
        wa_s_3.EOP  <= 1'b0;
end

//------------------------------------------------------------------------------------------//
//------------------------------------------------------------------------------------------//
//read_fsm
always_comb begin
    case(1'b1)
        ra_s.READY[0]:cur_cache_empty = (&s_cac_0.EMPTY);
        ra_s.READY[1]:cur_cache_empty = (&s_cac_1.EMPTY);
        ra_s.READY[2]:cur_cache_empty = (&s_cac_2.EMPTY);
        ra_s.READY[3]:cur_cache_empty = (&s_cac_3.EMPTY);
        ra_s.READY[4]:cur_cache_empty = (&s_cac_4.EMPTY);
        ra_s.READY[5]:cur_cache_empty = (&s_cac_5.EMPTY);
        ra_s.READY[6]:cur_cache_empty = (&s_cac_6.EMPTY);
        ra_s.READY[7]:cur_cache_empty = (&s_cac_7.EMPTY);
        default:      cur_cache_empty = 1'b1;
    endcase
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        read_st_c   <=  RDIDLE;
    end
    else 
        read_st_c   <= read_st_n;
end

always_comb begin
    read_st_n = read_st_c;
    case(read_st_c)
        RDIDLE:begin
            if(|ra_s.READY)
                read_st_n   =   RDJUDGE;
            else
                read_st_n   =   RDIDLE;
        end
        RDJUDGE:begin
            if(cur_cache_empty)begin
                read_st_n   =   JUMP;
            end
            else if((!cur_cache_empty) && dd_st_c == DDIDLE)
                read_st_n   =   RDGET_ADDR;
            else
                read_st_n   =   RDJUDGE;
        end
        RDGET_ADDR:begin
            if(dd_st_c==FLUSH)
                read_st_n   =   RDIDLE;
            else 
                read_st_n   =   BACK_ADDR;
        end
        BACK_ADDR:begin
            if(dd_st_c==FLUSH)
                read_st_n   =   RDIDLE;
            else
                read_st_n   =   RD;
        end
        RD:begin
            if((ra_s.RD_STATE==2'b11&&ra_s.RD_STATE_VLD)||dd_st_c==FLUSH)
                read_st_n   =   RDIDLE;
            else
                read_st_n   =   RD;
        end
        JUMP:begin
            read_st_n       =   RDIDLE;
        end
    endcase
end
assign  ra_s.PRIORITY_JMP = read_st_c == JUMP;
//---POP rd addr and size from fifo_ctrl
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        st_fifo_0.RD_EN <= '0;
    end
    else if(read_st_c == RDGET_ADDR && ra_s.READY[0] &&(dd_st_c!=FLUSH))begin
        st_fifo_0.RD_EN <= 1'b1;
    end
    else
        st_fifo_0.RD_EN <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        st_fifo_1.RD_EN <= '0;
    end
    else if(read_st_c == RDGET_ADDR && ra_s.READY[1]&&(dd_st_c!=FLUSH))begin
        st_fifo_1.RD_EN <= 1'b1;
    end
    else
        st_fifo_1.RD_EN <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        st_fifo_2.RD_EN <= '0;
    end
    else if(read_st_c == RDGET_ADDR && ra_s.READY[2]&&(dd_st_c!=FLUSH))begin
        st_fifo_2.RD_EN <= 1'b1;
    end
    else
        st_fifo_2.RD_EN <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        st_fifo_3.RD_EN <= '0;
    end
    else if(read_st_c == RDGET_ADDR && ra_s.READY[3]&&(dd_st_c!=FLUSH))begin
        st_fifo_3.RD_EN <= 1'b1;
    end
    else
        st_fifo_3.RD_EN <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        st_fifo_4.RD_EN <= '0;
    end
    else if(read_st_c == RDGET_ADDR && ra_s.READY[4]&&(dd_st_c!=FLUSH))begin
        st_fifo_4.RD_EN <= 1'b1;
    end
    else
        st_fifo_4.RD_EN <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        st_fifo_5.RD_EN <= '0;
    end
    else if(read_st_c == RDGET_ADDR && ra_s.READY[5]&&(dd_st_c!=FLUSH))begin
        st_fifo_5.RD_EN <= 1'b1;
    end
    else
        st_fifo_5.RD_EN <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        st_fifo_6.RD_EN <= '0;
    end
    else if(read_st_c == RDGET_ADDR && ra_s.READY[6]&&(dd_st_c!=FLUSH))begin
        st_fifo_6.RD_EN <= 1'b1;
    end
    else
        st_fifo_6.RD_EN <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        st_fifo_7.RD_EN <= '0;
    end
    else if(read_st_c == RDGET_ADDR && ra_s.READY[7]&&(dd_st_c!=FLUSH))begin
        st_fifo_7.RD_EN <= 1'b1;
    end
    else
        st_fifo_7.RD_EN <= 1'b0;
end
//---POP rd addr and size from fifo_ctrl
//---flush fifo when dd conflict read
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        st_fifo_0.FLUSH <= '0;
    end
    else if(ra_s.READY[0])begin
        st_fifo_0.FLUSH <= flush_fifo;
    end
    else
        st_fifo_0.FLUSH <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        st_fifo_1.FLUSH <= '0;
    end
    else if(ra_s.READY[1])begin
        st_fifo_1.FLUSH <= flush_fifo;
    end
    else
        st_fifo_1.FLUSH <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        st_fifo_2.FLUSH <= '0;
    end
    else if(ra_s.READY[2])begin
        st_fifo_2.FLUSH <= flush_fifo;
    end
    else
        st_fifo_2.FLUSH <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        st_fifo_3.FLUSH <= '0;
    end
    else if(ra_s.READY[3])begin
        st_fifo_3.FLUSH <= flush_fifo;
    end
    else
        st_fifo_3.FLUSH <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        st_fifo_4.FLUSH <= '0;
    end
    else if(ra_s.READY[4])begin
        st_fifo_4.FLUSH <= flush_fifo;
    end
    else
        st_fifo_4.FLUSH <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        st_fifo_5.FLUSH <= '0;
    end
    else if(ra_s.READY[5])begin
        st_fifo_5.FLUSH <= flush_fifo;
    end
    else
        st_fifo_5.FLUSH <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        st_fifo_6.FLUSH <= '0;
    end
    else if(ra_s.READY[6])begin
        st_fifo_6.FLUSH <= flush_fifo;
    end
    else
        st_fifo_6.FLUSH <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        st_fifo_7.FLUSH <= '0;
    end
    else if(ra_s.READY[7])begin
        st_fifo_7.FLUSH <= flush_fifo;
    end
    else
        st_fifo_7.FLUSH <= 1'b0;
end

//--back rd addr and size to rd addr_gen
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        ra_s.RD_VLD <= '0;
    end
    else if(read_st_c == BACK_ADDR)begin
        ra_s.RD_VLD <= 1'b1;
    end
    else
        ra_s.RD_VLD <= 1'b0;
end

always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        ra_s.DATA_ADDR <= '0;
        ra_s.DATA_SIZE <= '0;
    end
    else if(read_st_c == BACK_ADDR && ra_s.READY[0])begin
        ra_s.DATA_ADDR <= st_fifo_0.RD_DATA[27:10];
        ra_s.DATA_SIZE <= st_fifo_0.RD_DATA[9:0];
    end
    else if(read_st_c == BACK_ADDR && ra_s.READY[1])begin
        ra_s.DATA_ADDR <= st_fifo_1.RD_DATA[27:10];
        ra_s.DATA_SIZE <= st_fifo_1.RD_DATA[9:0];
    end
    else if(read_st_c == BACK_ADDR && ra_s.READY[2])begin
        ra_s.DATA_ADDR <= st_fifo_2.RD_DATA[27:10];
        ra_s.DATA_SIZE <= st_fifo_2.RD_DATA[9:0];
    end
    else if(read_st_c == BACK_ADDR && ra_s.READY[3])begin
        ra_s.DATA_ADDR <= st_fifo_3.RD_DATA[27:10];
        ra_s.DATA_SIZE <= st_fifo_3.RD_DATA[9:0];
    end
    else if(read_st_c == BACK_ADDR && ra_s.READY[4])begin
        ra_s.DATA_ADDR <= st_fifo_4.RD_DATA[27:10];
        ra_s.DATA_SIZE <= st_fifo_4.RD_DATA[9:0];
    end
    else if(read_st_c == BACK_ADDR && ra_s.READY[5])begin
        ra_s.DATA_ADDR <= st_fifo_5.RD_DATA[27:10];
        ra_s.DATA_SIZE <= st_fifo_5.RD_DATA[9:0];
    end
    else if(read_st_c == BACK_ADDR && ra_s.READY[6])begin
        ra_s.DATA_ADDR <= st_fifo_6.RD_DATA[27:10];
        ra_s.DATA_SIZE <= st_fifo_6.RD_DATA[9:0];
    end
    else if(read_st_c == BACK_ADDR && ra_s.READY[7])begin
        ra_s.DATA_ADDR <= st_fifo_7.RD_DATA[27:10];
        ra_s.DATA_SIZE <= st_fifo_7.RD_DATA[9:0];
    end
end
//--back rd addr and size to rd addr_gen

//--back rd addr and size to imc
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_cac_0.RD_DATA_VLD     <= '0;
        s_cac_0.RD_DATA_VALUE   <= '0;
    end
    else if(read_st_c == BACK_ADDR && ra_s.READY[0])begin
        s_cac_0.RD_DATA_VLD   <= 1'b1;
        s_cac_0.RD_DATA_VALUE <= {2'b00,st_fifo_0.RD_DATA};
    end
    else if(ra_s.RD_STATE==2'b11 && ra_s.READY[0]&&ra_s.RD_STATE_VLD)begin
        s_cac_0.RD_DATA_VLD   <= 1'b1;
        s_cac_0.RD_DATA_VALUE <= {2'b10,st_fifo_0.RD_DATA};
    end
    else if(dd_st_c==FLUSH)begin
        s_cac_0.RD_DATA_VLD   <= 1'b1;
        s_cac_0.RD_DATA_VALUE[29:28] <= 2'b11;     
    end
    else 
        s_cac_0.RD_DATA_VLD   <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_cac_1.RD_DATA_VLD     <= '0;
        s_cac_1.RD_DATA_VALUE   <= '0;
    end
    else if(read_st_c == BACK_ADDR && ra_s.READY[1])begin
        s_cac_1.RD_DATA_VLD   <= 1'b1;
        s_cac_1.RD_DATA_VALUE <= {2'b00,st_fifo_1.RD_DATA};
    end
    else if(ra_s.RD_STATE==2'b11 && ra_s.READY[1]&&ra_s.RD_STATE_VLD)begin
        s_cac_1.RD_DATA_VLD   <= 1'b1;
        s_cac_1.RD_DATA_VALUE <= {2'b10,st_fifo_1.RD_DATA};
    end
    else if(dd_st_c==FLUSH)begin
        s_cac_1.RD_DATA_VLD   <= 1'b1;
        s_cac_1.RD_DATA_VALUE[29:28] <= 2'b11;     
    end
    else 
        s_cac_1.RD_DATA_VLD   <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_cac_2.RD_DATA_VLD     <= '0;
        s_cac_2.RD_DATA_VALUE   <= '0;
    end
    else if(read_st_c == BACK_ADDR && ra_s.READY[2])begin
        s_cac_2.RD_DATA_VLD   <= 1'b1;
        s_cac_2.RD_DATA_VALUE <= {2'b00,st_fifo_2.RD_DATA};
    end
    else if(ra_s.RD_STATE==2'b11 && ra_s.READY[2]&&ra_s.RD_STATE_VLD)begin
        s_cac_2.RD_DATA_VLD   <= 1'b1;
        s_cac_2.RD_DATA_VALUE <= {2'b10,st_fifo_2.RD_DATA};
    end
    else if(dd_st_c==FLUSH)begin
        s_cac_2.RD_DATA_VLD   <= 1'b1;
        s_cac_2.RD_DATA_VALUE[29:28] <= 2'b11;     
    end
    else 
        s_cac_2.RD_DATA_VLD   <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_cac_3.RD_DATA_VLD     <= '0;
        s_cac_3.RD_DATA_VALUE   <= '0;
    end
    else if(read_st_c == BACK_ADDR && ra_s.READY[3])begin
        s_cac_3.RD_DATA_VLD   <= 1'b1;
        s_cac_3.RD_DATA_VALUE <= {2'b00,st_fifo_3.RD_DATA};
    end
    else if(ra_s.RD_STATE==2'b11 && ra_s.READY[3]&&ra_s.RD_STATE_VLD)begin
        s_cac_3.RD_DATA_VLD   <= 1'b1;
        s_cac_3.RD_DATA_VALUE <= {2'b10,st_fifo_3.RD_DATA};
    end
    else if(dd_st_c==FLUSH)begin
        s_cac_3.RD_DATA_VLD   <= 1'b1;
        s_cac_3.RD_DATA_VALUE[29:28] <= 2'b11;     
    end
    else 
        s_cac_3.RD_DATA_VLD   <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_cac_4.RD_DATA_VLD     <= '0;
        s_cac_4.RD_DATA_VALUE   <= '0;
    end
    else if(read_st_c == BACK_ADDR && ra_s.READY[4])begin
        s_cac_4.RD_DATA_VLD   <= 1'b1;
        s_cac_4.RD_DATA_VALUE <= {2'b00,st_fifo_4.RD_DATA};
    end
    else if(ra_s.RD_STATE==2'b11 && ra_s.READY[4]&&ra_s.RD_STATE_VLD)begin
        s_cac_4.RD_DATA_VLD   <= 1'b1;
        s_cac_4.RD_DATA_VALUE <= {2'b10,st_fifo_4.RD_DATA};
    end
    else if(dd_st_c==FLUSH)begin
        s_cac_4.RD_DATA_VLD   <= 1'b1;
        s_cac_4.RD_DATA_VALUE[29:28] <= 2'b11;     
    end
    else 
        s_cac_4.RD_DATA_VLD   <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_cac_5.RD_DATA_VLD     <= '0;
        s_cac_5.RD_DATA_VALUE   <= '0;
    end
    else if(read_st_c == BACK_ADDR && ra_s.READY[5])begin
        s_cac_5.RD_DATA_VLD   <= 1'b1;
        s_cac_5.RD_DATA_VALUE <= {2'b00,st_fifo_5.RD_DATA};
    end
    else if(ra_s.RD_STATE==2'b11 && ra_s.READY[5]&&ra_s.RD_STATE_VLD)begin
        s_cac_5.RD_DATA_VLD   <= 1'b1;
        s_cac_5.RD_DATA_VALUE <= {2'b10,st_fifo_5.RD_DATA};
    end
    else if(dd_st_c==FLUSH)begin
        s_cac_5.RD_DATA_VLD   <= 1'b1;
        s_cac_5.RD_DATA_VALUE[29:28] <= 2'b11;     
    end
    else 
        s_cac_5.RD_DATA_VLD   <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_cac_6.RD_DATA_VLD     <= '0;
        s_cac_6.RD_DATA_VALUE   <= '0;
    end
    else if(read_st_c == BACK_ADDR && ra_s.READY[6])begin
        s_cac_6.RD_DATA_VLD   <= 1'b1;
        s_cac_6.RD_DATA_VALUE <= {2'b00,st_fifo_6.RD_DATA};
    end
    else if(ra_s.RD_STATE==2'b11 && ra_s.READY[6]&&ra_s.RD_STATE_VLD)begin
        s_cac_6.RD_DATA_VLD   <= 1'b1;
        s_cac_6.RD_DATA_VALUE <= {2'b10,st_fifo_6.RD_DATA};
    end
    else if(dd_st_c==FLUSH)begin
        s_cac_6.RD_DATA_VLD   <= 1'b1;
        s_cac_6.RD_DATA_VALUE[29:28] <= 2'b11;     
    end
    else 
        s_cac_6.RD_DATA_VLD   <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_cac_7.RD_DATA_VLD     <= '0;
        s_cac_7.RD_DATA_VALUE   <= '0;
    end
    else if(read_st_c == BACK_ADDR && ra_s.READY[7])begin
        s_cac_7.RD_DATA_VLD   <= 1'b1;
        s_cac_7.RD_DATA_VALUE <= {2'b00,st_fifo_7.RD_DATA};
    end
    else if(ra_s.RD_STATE==2'b11 && ra_s.READY[7]&&ra_s.RD_STATE_VLD)begin
        s_cac_7.RD_DATA_VLD   <= 1'b1;
        s_cac_7.RD_DATA_VALUE <= {2'b10,st_fifo_7.RD_DATA};
    end
    else if(dd_st_c==FLUSH)begin
        s_cac_7.RD_DATA_VLD   <= 1'b1;
        s_cac_7.RD_DATA_VALUE[29:28] <= 2'b11;     
    end
    else 
        s_cac_7.RD_DATA_VLD   <= 1'b0;
end
//--back rd addr and size to imc

//dd fsm

assign  dir_del = ( (cc_s.WR_SOP0&&(!cc_s.DATA_STATUS0))||
                    (cc_s.WR_SOP1&&(!cc_s.DATA_STATUS1))||
                    (cc_s.WR_SOP2&&(!cc_s.DATA_STATUS2))||
                    (cc_s.WR_SOP3&&(!cc_s.DATA_STATUS3)) );
always_comb begin
   unique case(1'b0)
   cc_s.DATA_STATUS0:begin
       dd_pri = cc_s.DATA_PRI0;
       dd_eop = cc_s.WR_EOP0;
       dd_data= cc_s.WR_DATA0;
       dd_vld = cc_s.WR_VLD0;
   end
   cc_s.DATA_STATUS1:begin
       dd_pri = cc_s.DATA_PRI1;
       dd_eop = cc_s.WR_EOP1;
       dd_data= cc_s.WR_DATA1;
       dd_vld = cc_s.WR_VLD1;
   end
   cc_s.DATA_STATUS2:begin
       dd_pri = cc_s.DATA_PRI2;
       dd_eop = cc_s.WR_EOP2;
       dd_data= cc_s.WR_DATA2;
       dd_vld = cc_s.WR_VLD2;

   end
   cc_s.DATA_STATUS3:begin
       dd_pri = cc_s.DATA_PRI3;
       dd_eop = cc_s.WR_EOP3;
       dd_data= cc_s.WR_DATA3;
       dd_vld = cc_s.WR_VLD3;
   end
   default:begin
       dd_pri = '0;
       dd_eop = '0;
       dd_data= '0;
       dd_vld = '0;
   end
    endcase
end
always_comb begin
    unique case(ra_s.READY)
        8'b0000_0001:cur_pri = 3'b000;    
        8'b0000_0010:cur_pri = 3'b001;    
        8'b0000_0100:cur_pri = 3'b010;    
        8'b0000_1000:cur_pri = 3'b011;    
        8'b0001_0000:cur_pri = 3'b100;    
        8'b0010_0000:cur_pri = 3'b101;    
        8'b0100_0000:cur_pri = 3'b110;    
        8'b1000_0000:cur_pri = 3'b111;
        default     :cur_pri = '0;
endcase
end
always_ff @(posedge CLK or negedge RST_N) begin 
    if(!RST_N)begin
        dd_st_c <=  DDIDLE;
    end
    else 
        dd_st_c <=  dd_st_n;
end

always_comb begin
    dd_st_n = dd_st_c;
    case(dd_st_c)
        DDIDLE:begin
            if(dir_del)
                dd_st_n = JUDGE;
            else
                dd_st_n = DDIDLE;
        end
        JUDGE:begin
            if(dd_pri==cur_pri)
                dd_st_n = DIR_DEL;
            else
                dd_st_n = FLUSH;
        end
        FLUSH:begin
            if(ra_s.FLUSH_END)
                dd_st_n = DIR_DEL;
            else
                dd_st_n = FLUSH;
        end
        DIR_DEL:begin
            if(dd_eop)
                dd_st_n = DDIDLE;
            else
                dd_st_n = DIR_DEL;
        end
    endcase
end
assign flush_fifo   =   (dd_st_c==FLUSH) && (read_st_c == BACK_ADDR || read_st_c == RD);
assign ra_s.FLUSH_START = (!ra_s.FLUSH_END) && (dd_st_c==FLUSH);
assign  cc_s.PORT_READ  = ((read_st_c!= RDIDLE) && (read_st_c!=RDJUDGE) && (read_st_c!=JUMP)) || (dd_st_c != DDIDLE);
//assign  cc_s.PORT_READ  = (read_st_c!= RDIDLE) || (dd_st_c != DDIDLE);
//st to tx logic(dir deliver logic)
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_tx.WR_SOP <= '0;
    end
    else if(dd_st_c == JUDGE)begin
        s_tx.WR_SOP <= 1'b1;
    end
    else
        s_tx.WR_SOP <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_tx.WR_VLD <= '0;
    end
    else if(dd_st_c != DDIDLE)begin
        s_tx.WR_VLD <= dd_vld;
    end
    else
        s_tx.WR_VLD <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_tx.WR_DATA <= '0;
    end
    else if(dd_st_c != DDIDLE)begin
        s_tx.WR_DATA <= dd_data;
    end
    else
        s_tx.WR_DATA <= 1'b0;
end
always_ff @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        s_tx.WR_EOP <= '0;
    end
    else if(dd_st_c == DIR_DEL)begin
        s_tx.WR_EOP <= dd_eop;
    end
    else
        s_tx.WR_EOP <= 1'b0;
end
//-----dd_end-------------------

//------------------------------------------------------------------------------------------//


endmodule
